Z85233 Datasheet, PDF (313/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
Zilog SCC
SYNCHRONOUS MODES
(SDLC, HDLC, BYSYNC, AND MONOSYNC MODES INCLUDED)
Q. For what are the cyclical redundancy check (CRC)
residue codes used?
A. The residue codes provide a secondary method to
check the reception of the message.
Q. Why is the second byte of the CRC incorrect when
read from the receiving SCC?
A. The second byte of the CRC actually consists of the
last two bits of the first byte or CRC, and the first six
bits of the second byte of CRC.
Q. How does the SCC send CRC?
A. The SCC can be programmed to automatically send the
CRC. First, write the first byte of the message to be
sent. This guarantees the transmitter is full. Then reset
the Transmit Underrun/EOM latch (WR0 10). Write the
rest of the data frame. When the transmit buffer under-
runs, the CRC is sent. The following table describes the
action taken by the SCC for the bit-oriented protocols:
Tx Underrun
EOM Latch Bit
0
0
1
Abort/Flag Action Upon
Bit
Tx Underrun
0
Sends CRC +
Flags
0
Sends Abort +
Flags
X
Sends Flags
Comment
Valid Frame
Aborted
Frame
Software
CRC
The SCC sets the Tx Underrun/EOM latch when the CRC
or Abort is loaded into the shift register for transmission.
This event causes an interrupt (if enabled).
Q. If the SCC is idling flags, and a byte of data is
loaded into the transmit buffer, what will be
transmitted?
A. Data takes priority over flags and will be loaded in the
shift register and transmitted.
Q. Since data is preferred, can this cause a problem?
A. This allows you to append on the end of a message, but
it can cause problems with DMA. A character could be
transmitted without an opening flag. To make sure that
a flag has been transmitted, watch for the W/REQ line
to toggle when the flag is loaded into the shift register.
Q. Can you gate data by stretching the receive clock?
A. You can hold the clock until you have valid data. There
are no maximum specs on the RxC period, and the
edges are used to sample the data. If there are no edg-
es, no data is sampled.
Q. How do you synchronize the DPLL in SDLC mode?
A. There are two methods to synchronize the DPLL. Sup-
ply at least 16 transitions at the beginning of each
message so the DPLL has time to make adjustments,
or use the DPLL search mode in WR14 to cause the
SCC to synchronize on first transition. The first edge
must be guaranteed to be a cell boundary.
Q. In SDLC, is the flag and address stripped-off?
A. No, only the flag is stripped. The address will be the
1st character received.
Q. Does IBM^® SDLC specify parity?
A. No.
Q. In SDLC, when do you reset the CRC generator
and checker?
A. The Reset TxCRC Generator command should be is-
sued when the transmitter is enabled and idling
(WR0). This needs to be done only once at initializa-
tion time for SDLC mode.
Q. How can you make sure that a flag is transmitted
after CRC?
A. Use the external status end of message (EOM) inter-
rupt to start the CRC transmission, then enable the
transmit buffer empty interrupt. When you get the in-
terrupt, it means that the buffer is empty, a flag is load-
ed in the shift register, and you can send the next
packet of information.
Q. Can the SCC include parity in SDLC mode?
A. Yes. It is appended at the end of the character.
Q. How does the SCC operate in transparent mode?
A. The transparentness, as defined by IBM SNA, should
be provided by the software. The SCC does not per-
form any automatic insertion and deletion of link con-
trol nor does it automatically exclude the characters
from the CRC calculation. This also applies to other
high level protocols.
Q. When does the Abort function take effect?
A. The abort takes place immediately by inserting eight
consecutive 1’s.
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