Z85233 Datasheet, PDF (33/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
Interfacing the SCC/ESCC
2.3 Z85X30 INTERFACE TIMING (Continued)
2.3.5 Z85C30 Register Enhancement
The Z85C30 has an enhancement to the NMOS Z8530
register set, which is the addition of a 10x19 SDLC Frame
Status FIFO. When WR15 bit D2=1, the SDLC Frame Sta-
tus FIFO is enabled, and it changes the functionality of
RR6 and RR7. See Section 4.4.3 for more details on this
feature.
2.3.6 Z85C30/Z85230 Register
Enhancements
In addition to the enhancements mentioned in 2.3.5, the
85C30/85230 provides several enhancements to the SCC
register set. These include the addition of Write Register 7
Prime (WR7'), the ability to read registers that are write-
only in the SCC.
WR7' Prime
D7 D6 D5 D4 D3 D2 D1 D0
Auto Tx Flag
Auto EOM Reset
Auto/RTS Deactivation
Force TxD High
/DTR//REQ Fast Mode
Complete CRC Reception
Extended Read Enable
Reserved (Program as 0)
Figure 2-8b. Write Register 7 Prime for the 85C30
Write Register 7' is addressed by setting WR15, D0=1 and
then addressing WR7. Figure 2-8 shows the register bit lo-
cation of the six features enabled through this register for
the 85230, while Figure 2-7 shows the register bit location
for the 85C30. Note that the difference between the two
WR7' registers for the 85230 and the 85C30 is bit D5 and
bit D4. All writes to address seven are to WR7' when
WR15 D0=1. Refer to Chapter 5 for detailed information on
WR7'.
WR7'
D7 D6 D5 D4 D3 D2 D1 D0
Auto Tx Flag
Auto EOM Reset
Auto/RTS Deactivation
Rx FIFO Half Full
DTR/REQ Timing Mode
Tx FIFO Empty
Extended Read Enable
Reserved (Must be 0)
Figure 2-8a. Write Register 7 Prime (WR7')
for the 85230
Setting WR7' bit D6=1 enables the extended read register
capability. This allows the user to read the contents of
WR3, WR4, WR5, WR7' and WR10 by reading RR9, RR4,
RR5, RR14 and RR11, respectively. When WR7' D6=0,
these write registers are write-only.
Table 2-6 shows what functions are enabled for the vari-
ous combinations of register bit enables. See Table 2-5 for
the register address map with only the SDLC FIFO en-
abled and with both the extended read and SDLC FIFO
features enabled.
Table 2-6. Z85C30/Z85230 Register
Enhancement Options
WR15
WR7'
Bit D2 Bit D0 Bit D6
0
1
0
0
1
1
1
0
X
1
1
0
1
1
1
Functions Enabled
WR7' enabled only
WR7' with extended read
enabled
10x19 SDLC FIFO
enhancement enabled only
10x19 SDLC FIFO and WR7'
10x19 SDLC FIFO and WR7'
with extended read enabled
2-14
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