Z85233 Datasheet, PDF (170/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

Application Note
The Z180™ Interfaced with the SCC at MHZ
Address
Address Valid
7
/INTACK
/CE
/RD
D7-D0
Data Valid
Figure 10. SCC Read Cycle Timing
Write Cycle Timing
Figure 11 illustrates the SCC Write cycle timing. All
register addresses and /INTACK are stable throughout the
cycle. The timing specification of the SCC requires that the
/CE signal (and address) be stable when /RD is active.
Data is available to the SCC before the falling edge of /WR
and remains active until /WR goes inactive.
Address
/INTACK
Address Valid
/CE
/WR
D7-D0
Data Valid
Figure 11. SCC Write Cycle Timing
UM010901-0601
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