Z85233 Datasheet, PDF (102/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
Data Communication Modes
4.4.3 SDLC Frame Status FIFO
Summarizing the operation; data is received, assembled,
and loaded into the eight-byte FIFO before being trans-
This feature is not available on the NMOS version.
On the CMOS version and the ESCC, the ability to receive
ferred to memory by the DMA controller. When a flag is re-
ceived at the end of an SDLC frame, the frame byte count
4
high speed back-to-back SDLC frames is maximized by a _{from the 14-bit counter and five status bits are loaded into}
10-bit deep by 19-bit wide status FIFO. When enabled _{the status FIFO for verification by the CPU. The CRC check-}
(through WR15, bit D2), it provides a DMA the ability to _{er is automatically reset in preparation for the next frame}
continue to transfer data into memory so that the CPU can _{which can begin immediately. Since the byte count and sta-}
examine the message later. For each SDLC frame, a 14- _{tus are saved for each frame, the message integrity can be}
bit byte count and five status/error bits are stored. The byte _{verified at a later time. Status information for up to 10 frames}
count and status bits are accessed through Read Regis- _{can be stored before a status FIFO overrun occurs.}
ters 6 and 7. Read Registers 6 and 7 are only accessible
when the SDLC FIFO is enabled. The 10x19 status FIFO If a frame is terminated with an ABORT, the byte count will
is separate from the 8-byte Receive Data FIFO.
be loaded to the status FIFO and the counter reset for the
next frame.
When the enhancement is enabled, the status in Read
Register 1 (RR1) and byte count for the SDLC frame is FIFO Detail. For a better understanding of details of the
stored in the 10 x 19 bit status FIFO. This allows the DMA FIFO operation, refer to the block diagram in Figure 4-15.
controller to transfer the next frame into memory while the
CPU verifies the message was properly received.
UM010901-0601
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