Z85233 Datasheet, PDF (80/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
Data Communication Modes
Table 4-2. Transmit Bits per Character
to send clocking information (transmit clock) along with the
Bit 7
0
0
Bit 6
0
1
5 or less bits/character
7 bits/character
data in order to receive data correctly.
4 ^{There are two modem control signals associated with the}
transmitter provided by the SCC; /RTS and /CTS.
1
0
1
1
6 bits/character
8 bits/character
The /RTS pin is a simple output that carries the inverted
state of the RTS bit (D1) in WR5, unless the Auto Enables
Note: For five or less bits per character selection in WR5, the
following encoding is used in the data sent to the transmitter.
D is the data bit(s) to be sent.
mode bit (D5) is set in WR3. When Auto Enables is set, the
/RTS pin immediately goes Low when the RTS bit is set.
However, when the RTS bit is reset, the /RTS pin remains
D7 D6 D5 D4 D3 D2 D1 D0
1 1 1 1 0 0 0D
1 1 1 0 0 0DD
1 1 0 0 0DDD
1 0 0 0DDDD
0 0 0DDDDD
Sends one data bit
Sends two data bits
Sends three data bits
Sends four data bits
Sends five data bits
Low until the transmitter is completely empty and the last
stop bit has left the TxD pin. Thus, the /RTS pin may be
used to disable external drivers for the transmit data. The
/CTS pin is ordinarily a simple input to the CTS bit in RR0.
However, if Auto Enables mode is selected, this pin be-
comes an enable for the transmitter. That is, if Auto En-
ables is on and the /CTS pin is High, the transmitter is dis-
abled; the transmitter is enabled while the /CTS pin is Low.
An additional bit, carrying parity information, may be auto-
matically appended to every transmitted character by set- _{The initialization sequence for the transmitter in Asynchro-}
ting bit D0 of WR4 to 1. This bit is sent in addition to the _{nous mode is WR4 first to select the mode, then WR3 and}
number of bits specified in WR4 or by bit D1 of WR4. If this _{WR5 to select the various options. At this point the other}
bit is set to 1, the transmitter sends even parity and, if set _{registers should be initialized as necessary. When all of}
to 0, the parity is odd.
this is complete, the transmitter may be enabled by setting
The transmitter may be programmed to send a Break by
setting bit D4 of WR5 to 1. The transmitter will send con-
bit D3 of WR5 to 1. Note that the transmitter and receiver
may be initialized at the same time.
tiguous 0s from the first transmit clock edge after this com- _{4.2.1.1 Asynchronous transmit on the NMOS/CMOS}
mand is issued, until the first transmit clock edge after this _{On the NMOS/CMOS version of the SCC, characters are}
bit is reset. The transmit clock edges referred to here are _{loaded from the transmit buffer to the shift register where}
those that defined transmitted bit cell boundaries. Care _{they are given a start bit and a parity bit (as programmed),}
must be taken when Break is sent. As mentioned above, _{and are shifted out to the TxD pin. The transmit buffer}
the SCC initiates the Break sequence regardless of the _{empty interrupt and the DMA request (either /W//REQ or}
character boundaries. Typically, the break sequence is de- _{/DTR//REQ pin) are asserted when the transmit buffer is}
fined as “null character (all 0 data) with framing error”. The _{empty, if these are enabled. At this time, the CPU or the}
other party may not be able to recognize it as a break se- _{DMA is able to write one byte of transmit data. The Trans-}
quence if the Send Break bit has been set in the middle of _{mit Buffer Empty (TBE) bit (RR0, bit D2) also follows the}
sending a non-zero character.
state of the transmit buffer. The All Sent bit, RR1, bit D0,
An additional status bit for use in Asynchronous mode is
available in bit D0 of RR1. This bit, called All Sent, is set
when the transmitter is completely empty and any previous
data or stop bits have reached the TxD pin. The All Sent
can be polled to determine when the last bit of transmit
data has cleared the TxD pin. For details about the trans-
mit DMA and transmit interrupts, refer to Section 2.4.8
“Transmit Interrupt and Transmit Buffer Empty bit.”
bit can be used by the processor as an indication that the _{4.2.1.2 Asynchronous transmit on the ESCC}
transmitter may be safely disabled, or indication to change _{On the ESCC, characters are loaded from the Transmit}
the modem status signal.
FIFO to the shift register where they are given a start bit
The SCC may be programmed to accept a transmit clock
that is one, sixteen, thirty-two, or sixty-four times the data
rate. This is selected by bits D7 and D6 in WR4, in com-
mon with the clock factor for the receiver.
and a parity bit (as programmed), and are shifted out to the
TxD pin. The ESCC can generate an interrupt or DMA re-
quest depending on the status of the Transmit FIFO. If
WR7' D5 is reset, the transmit buffer empty interrupt and
DMA request (either /W//REQ or /DTR//REQ pin) are as-
Note: When using Isosynchronous (X1 clock) mode, one-
and-a-half stop bits are not allowed. Only one or two stop
bits should be selected. If some length other than one stop
bit is desired in the times one mode, only two stop bits may
be used. Also, in this mode, the Transmitter usually needs
serted when the entry location of the Transmit FIFO is
empty (one byte can be written). If WR7' D5 is set, the
transmit interrupt and DMA request is generated when the
Transmit FIFO is completely empty (four bytes can be writ-
ten). The Transmit Buffer Empty (TBE) bit in RR0, bit D2
also is affected by the state of WR7' bit D5. The All Sent
UM010901-0601
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