Z85233 Datasheet, PDF (171/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

Application Note
The Z180™ Interfaced with the SCC at MHZ
(Continued)
SCC Interrupt Operation
Understanding SCC interrupt operations requires a basic
knowledge of the Interrupt Pending (IP) and Interrupt
Under Service (IUS) bits in relation to the daisy chain. The
Z180 and SCC design allow no additional interrupt
requests during an Interrupt Acknowledge cycle. This
permits the interrupt daisy chain to settle, ensuring proper
response of the interrupt device.
The IP bit sets in the SCC for CPU intervention
requirements (that is, buffer empty, character available,
error detection, or status changes). The interrupt
acknowledge cycle does not reset the IP bit. The IP bit
clears by a software command to the SCC, or when the
action that generated the interrupt ends, for example,
reading a receive character for receive interrupt. Others
are, writing data to the transmitter data register, issuing
Reset Tx interrupt pending command for Tx buffer empty
interrupt, etc.). After servicing the interrupt, other interrupts
can occur.
The IUS bit means the CPU is servicing an interrupt. The
IUS bit sets during an Interrupt Acknowledge cycle if the IP
bit sets and the IEI line is High. If the IEI line is low, the IUS
bit is not set. This keeps the device from placing its vector
onto the data bus.
The IUS bit clears in the Z80 peripherals by decoding the
RETI instruction. A software command also clears the IUS
bit in the Z80 peripherals. Only software commands clear
the IUS bit in the SCC.
Z80 Interrupt Daisy-Chain Operation
In the Z80 peripherals, both IP and IUS bits control the IEO
line and the lower portion of the daisy chain. When a
peripheral’s IP bit sets, the IEO line goes low. This is true
regardless of the state of the IEI line. Additionally, if the
peripheral’s IUS bit clears and its IEI line is High, the /INT
line goes low.
The Z80 peripherals sample for both /M1 and /IORQ active
(and /RD inactive) to identify an Interrupt Acknowledge
cycle. When /M1 goes active and /RD is inactive, the
peripheral detects an Interrupt Acknowledge cycle and
allows its interrupt daisy chain to settle. When the /IORQ
line goes active with /M1 active, the highest priority
interrupting peripheral places its interrupt vector onto the
data bus. The IUS bit also sets to show that the peripheral
is now under service. As long as the IUS bit sets, the IEO
line remains low. This inhibits any lower priority devices
from requesting an interrupt.
When the Z180 CPU executes the RETI instruction, the
peripherals check the data bus and the highest priority
device under service resets its IUS bit.
SCC Interrupt Daisy-Chain Operation
In the SCC, the IUS bit normally controls the state of the
IEO line. The IP bit affects the daisy chain only during an
Interrupt Acknowledge cycle. Since the IP bit is normally
not part of the SCC interrupt daisy chain, there is no need
to decode the RETI instruction. To allow for control over
the daisy chain, the SCC has a Disable Lower Chain (DLC)
software command that pulls IEO low. This selectively
deactivates parts of the daisy chain regardless of the
interrupt status. Table 6 shows the truth table for the SCC
interrupt daisy chain control signals during certain cycles.
Table 12 shows the interrupt state diagram for the SCC.
Table 6. SCC Daisy Chain Signal Truth Table
During Idle State
IEI IP IUS
0XX
1X0
1X1
1
0
0
During INTACK Cycle
IEO IEI
0
0
1
1
0
1
1
IP IUS IEO
XX0
1X0
X
1
0
6-36
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