Z85233 Datasheet, PDF (52/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
Interfacing the SCC/ESCC
crystal option in External Sync mode is illegal, but the re- SDLC mode, the receiver automatically synchronizes on
sult will be the same.
Flag characters. The receiver is in Hunt mode when it is en-
abled, so the Enter Hunt command is never needed.
In Synchronous modes other than SDLC, the Sync/Hunt
2
reports the Hunt state of the receiver. Hunt mode is en- 2.4.9.6 External/Status Interrupt Handling
tered when the processor issues the Enter Hunt command If careful attention is paid to details, the interrupt service
in WR3. This forces the receiver to search for a sync char- routine for External/Status interrupts is straightforward. To
acter match in the receive data stream. Because both tran- determine which bit or bits changed state, the routine
sitions of the Hunt bit close the latches, issuing this com- should first read RR0 and compare it to a copy from mem-
mand will cause an External/Status interrupt. The SCC ory. For each changed bit, the appropriate action should
resets this bit when character synchronization has been be taken and the copy in memory updated. The service
achieved, causing the latches to again be closed.
routine should close with two Reset External/Status inter-
rupt commands to reopen the latches. The copy of RR0 in
In these synchronous modes, the SCC will not re-enter the _{memory should always have the Zero Count bit set to 0,}
Hunt mode automatically; only the Enter Hunt command will _{since this is the state of the bit after the Reset Exter-}
set this bit. In SDLC mode this bit is also set by the Enter _{nal/Status interrupts command at the end of the service}
Hunt command, but the receiver automatically enters the _{routine. When the processor issues the Reset Transmit}
Hunt mode if an Abort sequence is received. The receiver _{Underrun/EOM latch command in WR0, the Transmit Un-}
leaves Hunt upon receipt of a flag sequence. Both transi- _{derrun/EOM bit in the copy of RR0 in memory should be}
tions of the Hunt bit will cause the latches to be closed. In _{reset because this transition does not cause an interrupt.}
2.5 BLOCK/DMA TRANSFER
The SCC provides a Block Transfer mode to accommo-
date CPU block transfer functions and DMA controllers.
The Block Transfer mode uses the /W//REQ output in con-
junction with the Wait/Request bits in Write Register 1. The
/W//REQ output can be defined by software as a /WAIT
line in the CPU Block Transfer mode or as a /REQ line in
the DMA Block Transfer mode. The /DTR//REQ pin can
also be programmed through WR14 bit D2 to function as a
DMA request for the transmitter.
To a DMA controller, the SCC's /REQ outputs indicate that
the SCC is ready to transfer data to or from memory. To
the CPU, the /WAIT output indicates that the SCC is not
ready to transfer data, thereby requesting the CPU to ex-
tend the I/O cycle.
2.5.1 Block Transfers
The SCC offers several alternatives for the block transfer
of data. The various options are selected by WR1 (bits D7
through D5) and WR14 (bit D2). Each channel in the SCC
has two pins which are used to control the block transfer of
data. Both pins in each channel may be programmed to act
as DMA Request signals. The /W//REQ pin in each chan-
nel may be programmed to act as a Wait signal for the
CPU. In either mode, it is advisable to select and enable
the mode in two separate accesses of the appropriate reg-
ister. The first access should select the mode and the sec-
ond access should enable the function. This procedure
prevents glitches on the output pins. Reset forces Wait
mode, with /W//REQ open-drain.
2.5.1.1 Wait On Transmit
The Wait On Transmit function is selected by setting both
D6 and D5 to 0 and then enabling the function by setting
D7 of WR1 to 1. In this mode the /W//REQ pin carries the
/WAIT signal, and is open-drain when inactive and Low
when active. When the processor attempts to write to the
transmit buffer when it is full, the SCC asserts /WAIT until
the byte is written (Figure 2-24).
UM010901-06
01
2-33