Z85233 Datasheet, PDF (89/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
Data Communication Modes
4.3 BYTE-ORIENTED SYNCHRONOUS MODE (Continued)
Receive Data
Receive Data FIFO
3 Bytes Deep for NMOS/CMOS
8 Bytes Deep for ESCC
Receive Shift Register
Eight Bit Time Delay
CRC Checker
Figure 4-9. Receive CRC Data Path
Before A is received, the receiver is in Hunt mode and the
CRC is disabled. When A is in the receive shift register, it
is compared with the contents of WR7. Since A is the sync
character, the bit patterns match and receive leaves Hunt
mode, but character A is not transferred to the receive
data FIFO.
After eight-bit times, B is loaded into the receive data
FIFO. The CRC remains disabled even though some-
where during the next eight bit times the processor reads
B and enables the CRC. At the end of this eight-bit time, B
is in the 8-bit delay and C is in the receive shift register.
Character C is loaded into the receive data FIFO and at the
same time the CRC checker becomes enabled. During the
next eight-bit time, the processor reads C and since the
CRC is enabled within this period, the SCC has calculated
the CRC on B, character C is the 8-bit delay, and D is in
the Receive Shift register. D is then loaded into the receive
data FIFO and at some point during the next eight-bit time
the processor reads D and disables the CRC. At the end
of these eight-bit times, the CRC has been calculated on
C, character D is in the 8-bit delay, and E is in the Receive
Shift register.
Now E is loaded into the receive data FIFO. During the
next eight-bit time, the processor reads E and enables the
CRC. During this time E shifts into the 8-bit delay, F enters
the Receive Shift register and the CRC is not being calcu-
lated on D. After these eight-bit times have elapsed, E is in
the 8-bit delay, and F is in the Receive Shift register. Now
F is transferred to the receive data FIFO and the CRC is
enabled. During the next eight-bit times, the processor
reads F and leaves the CRC enabled. The processor de-
tects that this is the last character in the message and pre-
pares to check the result of the CRC computation. Howev-
er, another sixteen bit-times are required before the CRC
has been calculated on all of character F.
At the end of eight-bit times, F is in the 8-bit delay and G is
in the Receive Shift register. At this time, it is transferred to
the receive data FIFO. Character G is read and discarded
by the processor. Eight-bit times later, H is also transferred
to the receive data FIFO. The result of a CRC calculation
is latched in to the Receive Error FIFO at the same time as
data is written to the Receive Data FIFO. Thus, the CRC
result through character F accompanies character H in the
FIFO and will be valid in RR1 until character H is read from
the Receive Data FIFO. The CRC checker is disabled and
reset at any time after character H is transferred to the Re-
ceive Data FIFO. Recall, however, that internally the CRC
is not disabled until after this occurs. A better alternative is
to place the receiver in Hunt mode, which automatically
disables and resets the CRC checker. See Table 4-7 for a
condensed description.
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UM010901-0601