Z85233 Datasheet, PDF (42/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
Interfacing the SCC/ESCC
When these bits indicate that a received character has On the ESCC with D3=1, four bytes are accumulated in the
reached the exit location of the FIFO, the status in RR1 Receive FIFO before an interrupt is generated (IP is set),
2 ^{should be checked and then the data should be read. If and reset when the number of the characters in the FIFO}
status is to be checked, it must be done before the data is is less than four.
read, because the act of reading the data pops both the
data and error FIFOs.
The special receive conditions are identical to those previ-
ously mentioned, and as before, the only difference be-
2.4.7.3 Receive Interrupt on First Character or Special tween a “receive character available” interrupt and a “spe-
Condition
cial receive condition” interrupt is the status encoded in the
This mode is designed for use with DMA transfers of the vector. In this mode a special receive condition does not
receive characters. The processor is interrupted when the lock the receive data FIFO so that the service routine must
SCC receives the first character of a block of data. It reads read the status in RR1 before reading the data.
the character and then turns control over to a DMA device
to transfer the remaining characters. After this mode is se- ^{At moderate to high data rates where the interrupt over-}
lected, the first character received, or the first character al- ^{head is significant, time can usually be saved by checking}
ready stored in the FIFO, sets the receiver IP. This IP is re- ^{for another character before exiting the service routine.}
set when this character is removed from the SCC.
This technique eliminates the interrupt acknowledge and
the status processing, saving time, but care must be exer-
No further receive interrupts occur until the processor is- cised because this receive character must be checked for
sues an Enable Interrupt on Next Receive Character com- special receive conditions before it is removed from
mand in WR0 or until a special receive condition occurs. the SCC.
The correct sequence of events when using this mode is
to first select the mode and wait for the receive character ^{2.4.7.5 Receive Interrupt on Special Conditions}
available interrupt. When the interrupt occurs, the proces- ^{This mode is designed for use when a DMA transfers all}
sor should read the character and then enable the DMA to ^{receive characters between memory and the SCC. In this}
transfer the remaining characters.
mode, only receive characters with special conditions will
cause the receive IP to be set. All other characters are as-
ESCC:
sumed to be transferred via DMA. No special initialization
WR7' bit D3 should be reset to zero in this mode.
sequence is needed in this mode. Usually, the DMA is ini-
tialized and enabled, then this mode is selected in the
A special receive condition interrupt may occur any time _{SCC. A special receive condition interrupt may occur at}
after the first character is received, but is guaranteed to oc- _{any time after this mode is selected, but the logic guaran-}
cur after the character having the special condition has _{tees that the interrupt will not occur until after the character}
been read. The status is not lost in this case, however, be- _{with the special condition has been read from the SCC.}
cause the FIFO is locked by the special condition. In the in- _{The special condition locks the FIFO so that the status is}
terrupt service routine, the processor should read RR1 to _{valid when read in the interrupt service routine, and it guar-}
obtain the status, and may read the data again if neces- _{antees that the DMA will not transfer any characters until}
sary. The FIFO is unlocked by issuing an Error Reset com- _{the special condition has been serviced.}
mand in WR0. If the special condition was End-of-Frame,
the processor should now issue the Enable Interrupt on In the service routine, the processor should read RR1 to
Next Receive Character command to prepare for the next obtain the status and unlock the FIFO by issuing an Error
frame. The first character interrupt and special condition Reset command. DMA transfer of the receive characters
interrupt are distinguished by the status included in the in- then resumes. Figure 2-15 shows the special conditions
terrupt vector. In all other respects they are identical, in- interrupt service routine.
cluding sharing the IP and IUS bits.
Note: On the CMOS and ESCC, if the SDLC Frame Status
2.4.7.4 Interrupt on All Receive Characters or Special FIFO is being used, please refer to Section 4.4.3 on the
Condition
FIFO anti-lock feature.
This mode is designed for an interrupt driven system. In
this mode, the NMOS/CMOS version and the ESCC with ^{Note: Special Receive Condition interrupts are generated}
WR7' D3=0 sets the receive IP when a received character ^{after the character is read from the FIFO, not when the}
is shifted into the exit location of the FIFO. This occurs ^{special condition is first detected. This is done so that}
whether or not it has a special receive condition. This in- ^{when using receive interrupt on first or Special Condition}
cludes characters already in the FIFO when this mode is ^{or Special Condition Only, data is directly read out of the}
selected. In this mode of operation the IP is reset when the ^{data FIFO without checking the status first. If a special}
character is removed from the FIFO, so if the processor re- ^{condition interrupted the CPU when first detected, it would}
quires status for any characters, this status must be read ^{be necessary to read RR1 before each byte in the FIFO to}
before the data is removed from the FIFO.
determine which byte had the special condition. Therefore,
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