Z85233 Datasheet, PDF (204/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

Application Note
The Zilog Datacom Family with the 80186 CPU
Table 8. On-Board Line Driver/Receiver Connectors
To use a serial chip controller with the
following on-chip serial interface:
J1A or J1B EIA-RS-232 Console
J2A or J2B EIA-RS-232
RS-422 differential: J3A or J3B EIA-530 or J4 Circular-8 (DIN)
Connect the connector(s)
from the previous table to:
8
J13
J14
J15
The pin-out of the J5-J10 connectors is fairly consistent, among the various serial controllers:
but of necessity not identical because of differences
Table 9. Pin Assignments of Standard Controller Connectors
J5: (E)SCC J6: (E)SCC
J7,8: ISCC
J9: IUSC
J10: MUSC
J12: USC
Pin# A pin
B pin
pin
pin
or USC A pin B pin
1
TxD
TxD
TxD
TxD
TxD
TxD
2
RxD
RxD
RxD
RxD
RxD
RxD
3
/RTS
/RTS
/RTS
(N/C)
/RxACK
/RxACK
4
/CTS
/CTS
/CTS
5
/DTR
/DTR or (N/C) [1] /DTR
6
/DCD
/DCD
/DCD
7
/SYNC
/SYNC
/SYNC
8
/RTxC
/RTxC
/RTxC
/CTS
(N/C)
/DCD
(SYSCLK)
/RxC
/CTS
/TxACK
/DCD
(SYSCLK)
/RxC
/CTS
/TxACK
/DCD
(SYSCLK)
/RxC
9
/TRxC
/TRxC
/TRxC
/TxC
/TxC
/TxC
10
GND
GND
GND
GND
GND
GND
11
NA
NA
NA
/TxREQ
/TxREQ
/TxREQ
12
NA
NA
NA
/RxREQ
/RxREQ
/RxREQ
Note:
[1] Controlled by the J24 jumper block: must be N/C if (E)SCC channel B transmitter is to be handled by an 80186 DMA channel.
The ground pins are included as signal references with off- enough opposing inputs and outputs as needed to make
board hardware.
the communication protocol meaningful.
When interconnecting between two connectors among J5-
J10, DO NOT jumper corresponding pins straight across,
as this connects outputs to outputs and inputs to inputs.
Rather, connect at least each pin 1 to the other pin 2, and
The pin-out of the 12-pin J13-J15 connectors is similar to
that of J5-J10, but more extensive. To allow for the “DCE”
connectors that were added in revision “B” of the board,
J13 and J14 are 16-pin headers and J15 is a 14-pin one:
Table 10. Pin Assignments of Line Driver/Receiver Connectors
J13-J14
J13-J14
J15
J15
Pin # DTE signal
DCE signal
DTE signal
DCE signal
Direction/where used
1
TxD
2
RxD
3
/RTS
4
/CTS
5
/DTR
6
/DSR
RxD
TxD
/CTS
/RTS
/DSR
/DTR
TxD
RxD
/RTS
/CTS
/DTR
/DSR
RxD
TxD
/CTS
/RTS
/DSR
/DTR
Output to J1-J4
Input from J1-J4
Output to J1-J3
Input from J1-J4 [3]
Output to J1-J4
Input from J1-J4
Note:
[3] Various conventions have been used to combine synchronous clock inputs and modem control inputs on Apple Macintosh connectors
similar to J4, as described in a later section.
UM010901-0601
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