Z85233 Datasheet, PDF (114/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
Register Descriptions
5.2.3 Write Register 2 (Interrupt Vector)
Bits 7 and 6: Receiver Bits/Character
WR2 is the interrupt vector register. Only one vector
register exists in the SCC, and it can be accessed through
either channel. The interrupt vector can be modified by
status information. This is controlled by the Vector
Includes Status (VIS) and the Status High/Status Low bits
in WR9. The bit positions for WR2 are shown in Figure 5-4.
The state of these two bits determines the number of bits
to be assembled as a character in the received serial data
stream. The number of bits per character can be changed
while a character is being assembled, but only before the
number of bits currently programmed is reached. Unused
bits in the Received Data Register (RR8) are set to 1 in
asynchronous modes. In Synchronous and SDLC modes,
5
the SCC merely transfers an 8-bit section of the serial data
Write Register 2
stream to the Receive FIFO at the appropriate time. Table
5-4 lists the number of bits per character in the assembled
D7 D6 D5 D4 D3 D2 D1 D0
character format.
V0
V1
V2
V3
Interrupt
V4
Vector
V5
V6
V7
Figure 5-4. Write Register 2
5.2.4 Write Register 3 (Receive Parameters
and Control)
This register contains the control bits and parameters for
the receiver logic as illustrated in Figure 5-5. On the ESCC
and 85C30, with the Extended Read option enabled, this
register may be read as RR9.
Write Register 3
D7 D6 D5 D4 D3 D2 D1 D0
0 0 Rx 5 Bits/Character
0 1 Rx 7 Bits/Character
1 0 Rx 6 Bits/Character
1 1 Rx 8 Bits/Character
Rx Enable
Sync Character Load Inhibit
Address Search Mode (SDLC)
Rx CRC Enable
Enter Hunt Mode
Auto Enables
Figure 5-5. Write Register 3
Table 5-4. Receive Bits per Character
D7
D6
Bits/Character
0
0
5
0
1
7
1
0
6
1
1
8
Bit 5: Auto Enable
This bit programs the function for both the /DCD and /CTS
pins. /CTS becomes the transmitter enable and /DCD be-
comes the receiver enable when this bit is set to 1. How-
ever, the Receiver Enable and Transmit Enable bits must
be set before the /DCD and /CTS pins can be used in this
manner. When the Auto Enable bit is set to 0, the /DCD
and /CTS pins are inputs to the corresponding status bits
in Read Register 0. The state of /DCD is ignored in the Lo-
cal Loopback mode. The state of /CTS is ignored in both
Auto Echo and Local Loopback modes.
Bit 4: Enter Hunt Mode
This command forces the comparison of sync characters
or flags to assembled receive characters for the purpose
of synchronization. After reset, the SCC automatically en-
ters the Hunt mode (except asynchronous). Whenever a
flag or sync character is matched, the Sync/Hunt bit in
Read Register 0 is reset and, if External/Status Interrupt
Enable is set, an interrupt sequence is initiated. The SCC
automatically enters the Hunt mode when an abort condi-
tion is received or when the receiver is enabled.
Bit 3: Receiver CRC Enable
This bit is used to initiate CRC calculation at the beginning
of the last byte transferred from the Receiver Shift register
to the Receive FIFO. This operation occurs independently
of the number of bytes in the Receive FIFO. When a par-
ticular byte is to be excluded from the CRC calculation, this
bit should be reset before the next byte is transferred to the
Receive FIFO. If this feature is used, care must be taken
to ensure that eight bits per character is selected in the re-
ceiver because of an inherent delay from the Receive Shift
register to the CRC checker.
UM010901-0601
5-7