Z85233 Datasheet, PDF (14/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
General Description
1.3 BLOCK DIAGRAM
Figure 1-1 has the block diagram of the SCC. Note that the
depth of the FIFO differs depending on the version. The
10X19 SDLC Frame Status FIFO is not available on the
NMOS version of the SCC.
Detailed internal signal path will be discussed in Chapter 4.
Channel A
Exploded Vie
Transmit Log
Transmit FIFO
NMOS/CMOS: 1 by
ESCC: 4 Bytes
Transmit MU
Data Encoding & CR
Generation
Receive and Transmit Clock Mult
Digital
Phase-Locke
Loop
Baud Rate
Generato
Crystal
Oscillato
Amplifie
Modem/Control Lo
Receive Log
Rec. Status*Rec. Data*
FIFO
FIFO
Receive MU
SDLC Frame Status F
10 x 19
** See No
CRC Checker
Data Decode &
Sync Charact
Detection
* NMOS/CMOS: 3 bytes each
ESCC: 8 bytes
** Not Available on NMOS
Interna
Contro
Logic
Channel A
Register
Databus
Contro
CPU & DMA
Bus Interfac
Interru
Contro
/INT
/INTAC
IEI
IEO
Interrup
Control
Logic
Channel B
Register
Figure 1-1. SCC Block Diagram
TxDA
/TRxCA
/RTxCA
/CTSA
/DCDA
/SYNCA
/RTSA
/DTRA//REQ
RxDA
Channel A
Channel B
1-4
UM010901-0601