Z85233 Datasheet, PDF (164/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

Application Note
The Z180™ Interfaced with the SCC at MHZ
inserting wait states. With this scheme, you can get the (Z180 parameter #24; 15 ns min at 10 MHz). It is stable
highest performance with moderate cost.
throughout the write cycle (Z180 parameter #27; 10 ns min
7 ^{at 10 MHz). Further, the address is fixed before the falling}
SRAM Write Cycle. During a Z180 memory write cycle, _{edge of /WR. As long as the /WR pulse width meets the}
the Z180 write data is stable before the falling edge of /WR _{SRAM’s spec, there is no problem (reference Table 2).}
T1
T2
Tw
T3
T1
Ø
Address
6
/MREQ
8
/WR
11
12
22
25
26
Data
24
27
23
Figure 3. Z180 Memory Write Cycle Timing (One Wait State)
Memory Interface Logic
The memory devices (EPROM and SRAM) for this design
are 256K bit (32K byte). There are two possible memory
interface designs:
Connect Address Decode output to /E input. Put the
signal generated by /RD and /MREQ ANDed together to
/OE of EPROM and SRAM. Put the signal generated by
/WR and /MREQ ANDed together to the /WE pin of
SRAM (Figure 4a).
Connect the signal Address ANDed together with inactive
/IORQ to the /E input. Connect /RD to /OE of EPROM and
SRAM, and /WR to /WE pin of SRAM (Figure 4b).
Using the second method, there could be a narrow glitch
on the signal to the /E-pin during I/O cycles and the
Interrupt acknowledge cycle. During I/O cycles, /IORQ and
/RD or /WR go active at almost the same time. Since the
delay times of these signals are similar there is no
“overlapping time” between /CE generated by the address
(/IORQ inactive), and /WR or /RD active. During the
Interrupt Acknowledge cycle, /WR and /RD signals are
inactive.
To keep the design simple and flexible, use the second
method (Figure 4b). To expand memory, decode the
address A15 NANDed with /USRRAM//USRROM and
/IORQ to produce /CSRAM or /CSROM. These are chip
select inputs to chips 55257 or 27C256, respectively. This
either disables or enables on-board ROM or RAM
depending upon selection control.
The circuit on Figure 4b gives the physical memory
address as shown on Figure 5.
If there are no Z80 peripherals and /M1 is enabled (M1E
bit in Z180 OMCR register set to 1), active wait states
occur only during opcode fetch cycles (Figure 6). If the
M1E bit is cleared to 0, /M1E is active only during the
Interrupt Acknowledge cycle and Return from Interrupt
cycle. This case depends on the propagation delay of the
address decoder which uses 135 ns or faster EPROM
assess time (assume there is 20 ns propagation delay).
Figure 6 shows the example of this implementation.
UM010901-0601
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