Z85233 Datasheet, PDF (48/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
Interfacing the SCC/ESCC
Last Data -1
Last Data
CRC1
CRC2
Flag
2
TBE
Set if Tx FIFO is Empty
Tx Underrun /EOM
When Auto EOM Reset has enabled
TxIP
Indicating CRC get loaded
Reset Tx Underrun/EOM Latch Command
If TxIP Reset Command
NOT Issued
TxIP Reset Command
to Clear Tx Interrupt
Data can be written to Tx FIFO after this point
Figure 2-21. Operation of TBE, Tx Underrun/EOM and TxIP on ESCC
An example flowchart for processing an end of packet is
shown in Figure 2-22. The chart includes the differences in
processing between the ESCC and NMOS/CMOS version.
In this chart, Tx IP and Underrun/EOM INT can be
processed by interrupts or by polling the registers. Note
that this flowchart does not have the procedures for
interrupt handling, such as saving/restoring of registers to
be used in the ISR (Interrupt Service Routine), Reset IUS
command, or return from interrupt sequence.
UM010901-06
01
2-29