Z85233 Datasheet, PDF (151/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

Application Note
Interfacing Z80^® CPUs to the Z8500 Peripheral Family
EXTERNAL INTERFACE LOGIC (Continued)
Figure 9. Z80A/Z80B CPU to Z8500/Z8500A Peripheral Interrupt Acknowledge Interface Logic
During I/O and normal memory access cycles, the Shift
registers remains cleared because the /M1 signal is
inactive. During opcode fetch cycles, also, the Shift
register remains cleared, because only 0s can be clocked
through the register. Since Shift register outputs are Low,
/READ, /WRITE, and /WAIT are controlled by other
system logic and gated through the AND gates (74LS11).
During I/O and normal memory access cycles, /READ and
/WRITE are active as a result of the system /RD and /WR
signals (respectively) becoming active. If system logic
requires that the CPU be placed into a Wait condition, the
/WAIT signal controls the CPU. Should it be necessary to
reset the system, /RESET causes the interface logic to
generate both /READ and /WRITE (the Z8500 peripheral
Reset condition).
Normally an Interrupt Acknowledge cycle is indicated by
the Z80 CPU when /M1 and /IORQ are both active (which
can be detected on the third rising clock edge after T1). To
obtain an early indication of an Interrupt Acknowledge
cycle, the Shift register decodes an active /M1 in the
presence of an inactive /MREQ on the rising edge of T2.
During an Interrupt Acknowledge cycle, the /INTACK
signal is generated on the rising edge of T2.
Since it is the presence of /INTACK and an active /READ
that gates the interrupt vector onto the data bus, the logic
must also generate /READ at the is Td1Ai(RD) /INTACK to
/RD (Acknowledge) Low Delay]. This time delay allows the
interrupt daisy chain to settle so that the device requesting
the interrupt can place its interrupt vector onto the data
bus. The shift register allows a sufficient time delay from
the generation of /INTACK before it generates /READ.
During this delay, it places the CPU into a Wait state until
the valid interrupt vector can be placed onto the data bus.
If the time between these two signals is insufficient for
daisy chain settling, more time can be added by taking
/READ and /WAIT from a later position on the Shift
register.
Figure 10 illustrates Interrupt Acknowledge cycle timing
resulting from the Z80A CPU to Z8500 peripheral and the
Z80B CPU to A8500A peripheral interface. This timing
comes from the logic illustrated in Figure 9, which can be
used for both interfaces. Should more Wait states be
required, the additional time can be calculated in terms of
system clocks, since the CPU clock and PCLK are the
same.
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