Z85233 Datasheet, PDF (105/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
Data Communication Modes
4.3 BYTE-ORIENTED SYNCHRONOUS MODE (Continued)
When a character with a special receive condition other
than EOF is received (receive overrun, or parity), a special
receive condition interrupt is generated after the character
is read from the FIFO and the Receive FIFO is locked until
the Error Reset command is issued.
4.4.4 SDLC Loop Mode
The SCC supports SDLC Loop mode in addition to normal
SDLC. SDLC Loop mode is very similar to normal SDLC
but is usually used in applications where a point-to-point
network is not appropriate (for example, Point-of-Sale ter-
minals). In an SDLC Loop, there is a primary controller that
manages the message traffic flow on the loop and any
number of secondary stations. In SDLC Loop mode, the
SCC operating in regular SDLC mode can act as the pri-
mary controller.
A secondary station in an SDLC Loop is always listening
to the messages being sent around the loop, and in fact
must pass these messages to the rest of the loop by re-
transmitting them with a one-bit-time delay.
The secondary station can place its own message on the
loop only at specific times. The controller signals that sec-
ondary stations may transmit messages by sending a spe-
cial character, called an EOP (End of Poll), around the
loop. The EOP character is the bit pattern 11111110.
When a secondary station has a message to transmit and
recognizes an EOP on the line, it changes the last binary
1 of the EOP to a 0 before transmission. This has the effect
of turning the EOP into a flag pattern. The secondary sta-
tion now places its message on the loop and terminates its
message with an EOP. Any secondary stations further
down the loop with messages to transmit can append their
messages to the message of the first secondary station by
the same process.
All secondary stations without messages to send merely
echo the incoming messages and are prohibited from
placing messages on the loop, except upon recognizing
an EOP.
SDLC Loop mode is quite similar to normal SDLC mode
except that two additional control bits are used. Writing a 1
to the Loop Mode bit in WR10 configures the SCC for Loop
mode. Writing a 1 to the Go Active on Poll bit in the same
register normally causes the SCC to change the next EOP
into a flag and then begin transmitting on loop. However,
when the SCC first goes on loop it uses the first EOP as a
signal to insert the one-bit delay, and doesn’t begin trans-
mitting until it receives the second EOP. There are also
two additional status bits in RR10, the On-Loop bit and the
Loop-Sending bit.
There are also restrictions as to when and how a second-
ary station physically becomes part of the loop.
A secondary station that has just powered up must monitor
the loop, without the one-bit-time delay, until it recognizes
an EOP. When an EOP is recognized the one-bit-time de-
lay is switched on. This does not disturb the loop because
the line is marking idle between the time that the controller
sends the EOP and the time that it receives the EOP back.
The secondary station that has gone on-loop cannot place
a message on the loop until the next time that an EOP is
issued by the controller. A secondary station goes off loop
in a similar manner. When given a command to go off-loop,
the secondary station waits until the next EOP to remove
the one-bit-time delay.
To operate the SCC in SDLC Loop mode, the SCC must
first be programmed just as if normal SDLC were to be
used. Loop mode is then selected by writing the appropri-
ate control word in WR10.
The SCC is now waiting for the EOP so that it can go on
loop. While waiting for the EOP, the SCC ties TxD to RxD
with only the internal gate delays in the signal path. When
the first EOP is recognized by the SCC, the
Break/Abort/EOP bit is set in RR0, generating an Exter-
nal/Status interrupt (if so enabled). At the same time, the
On-Loop bit in RR10 is set to indicate that the SCC is in-
deed on-loop, and a one-bit time delay is inserted in the
TxD to the RxD path.
The SCC is now on-loop but cannot transmit a message
until a flag and the next EOP are received. The require-
ment that a flag be received ensures that the SCC cannot
erroneously send messages until the controller ends the
current polling sequence and starts another one.
If the CPU in the secondary station with the SCC needs to
transmit a message, the Go-Active-On-Poll bit in WR10 is
set. If this bit is set when the EOP is detected, the SCC
changes the EOP to a flag and starts sending another flag.
The EOP is reported in the Break/Abort/EOP bit in RR0
and the CPU writes its data bytes to the SCC, just as in
normal SDLC frame transmission. When the frame is com-
plete and CRC has been sent, the SCC closes with a flag
and reverts to One-Bit-Delay mode. The last zero of the
flag, along with the marking line echoed from the RxD pin,
form an EOP for secondary stations further down the loop.
While the SCC is actually transmitting a message, the
loop-sending bit in R10 is set to indicate this.
If the Go-Active-On-Poll bit is not set at the time the EOP
passes by, the SCC cannot send a message until a flag
(terminating the current polling sequence) and another
EOP are received.
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