Z85233 Datasheet, PDF (101/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
Data Communication Modes
4.3 BYTE-ORIENTED SYNCHRONOUS MODE (Continued)
selected, the processor must issue an Error Reset com- Up to two modem control signals associated with the re-
mand in WR0 to unlock the Receive FIFO.
ceiver are available in SDLC mode:
In addition to searching the data stream for flags, the re-
ceiver in the SCC also watches for seven consecutive 1s,
which is the abort condition. The presence of seven con-
secutive 1s is reported in the Break/Abort bit in RR0. This
is one of the possible external/status interrupts, so transi-
tions of this status may be programmed to cause inter-
rupts. Upon receipt of an abort the receiver is forced into
Hunt mode where it looks for flags. The Hunt status is also
a possible external/status condition whose transition may
be programmed to cause an interrupt. The transitions of
these two bits occur very close together, but either one or
two external/status interrupts may result. The abort condi-
tion is terminated when a 0 is received, either by itself or
as the leading 0 of a flag. The receiver does not leave Hunt
mode until a flag has been received, so two discrete exter-
nal/status conditions occur at the end of an abort. An abort
received in the middle of a frame terminates the frame re-
ception, but not in an orderly manner because the charac-
ter being assembled is lost.
s The /DTR//REQ pin carries an inverted state of the DTR
bit (D7) in WR5 unless this pin has been programmed to
carry a DMA Request signal.
s The /DCD pin is ordinarily a simple input to the DCD bit
in RR0. However, if the Auto Enables mode is selected
by setting bit D5 of WR3 to 1, this pin becomes an
enable for the receiver. That is, if Auto Enables is on and
the /DCD pin is High, the receiver is disabled. While the
/DCD pin is Low, the receiver is enabled.
SDLC Initialization. The initialization sequence for SDLC
mode is WR4 to select SDLC mode first, WR3 and WR5 to
select the various options, WR7 to program flag, and then
WR6 for the receive address. At this point the other regis-
ters should be initialized as necessary. When all this is
completed the receiver is enabled by setting bit D0 of WR3
to a one. A summary is shown in Table 4-11.
Table 4-11. Initializing in SDLC Mode
Bit #
Reg
WR4
D7 D6 D5 D4 D3 D2 D1 D0
00100000
Description
Select x1 clock,
SDLC mode, enable sync mode
WR3 r x 0 1 1 1 0 0 rx=# of Rx bits/char, No auto enable, enter Hunt.
Enable Rx CRC, Address Search, No sync character
load inhibit
WR5 d t x 0 0 0 r 1 d=inverse of DTR pin, tx=# of Tx bits/char, use SDLC CRC,
r=inverse state of /RTS pin, CRC enable
WR7 0 1 1 1 1 1 1 0 SDLC Flag
WR6 x x x x x x x x Receiver secondary address
WR15 x x x x x x x 1 Enable access to new register
WR7' 0 1 1 d 1 r 1 1 Enable extended read, Tx INT on FIFO empty,
d=REQUEST timing mode, Rx INT on 4 char, r=RTS
deactivation, auto EOM reset, auto flag tx CRC preset to
zero, NRZ data,i=idle line
WR10 0 0 0 0 i 0 0 0 CRC preset to zero, NRZ data, i=idle line
WR3 r x 0 1 1 1 0 1
WR5 d t x 0 1 0 r 1
WR0 1 0 0 0 0 0 0 0
Note: The receiver searches for synchronization when it is in
Hunt mode. In this mode, the receiver is idle except for searching
the data stream for a flag match.
Enable Receiver
Enable Transmitter
Reset CRC generator
Note: The SYNC/HUNT bit in RR0 reports the Hunt Status, and
an interrupt is generated upon transitions between the Hunt state
and the Sync state.
Note: When the receiver detects a flag match it achieves syn- Note: The SCC will drive the /SYNC pin Low for one receive clock
chronization and interprets the following byte as the address field. cycle to signal that the flag has been received.
4-26
UM010901-0601