Z85233 Datasheet, PDF (195/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

Application Note
The Zilog Datacom Family with the 80186 CPU
GENERAL DESCRIPTION (Continued)
Processor
The 80186 may be operated at rates up to 16 MHz. To use
the CPU clock for accurate serial bit clocking, a 9.8304
MHz CPU clock can be used. The crystal connected to the
processor is 2X the operating frequency.
The processor’s 1 Mbyte address space is well filled if the
maximum RAM complement is installed. Of the integrated
Chip Select outputs provided by the 80186, the /UCS
output is used for the EPROMs, and all of the /PCS6-
/PCS0 outputs are used for the datacom controllers. A
hardware address decoder is used for the SRAMs instead
of the 80186’s /LCS and /MCS3-/MCS0 outputs because
the RAMs must be accessible to the on-chip DMA
functions of the ISCC and IUSC as well as the 80186. The
80186 does not decode addresses from external bus
masters. Both 8-bit and 16-bit accesses are provided for
RAM. The EPROMs are only accessible to the 80186.
The 80186’s mid-range memory chip select feature
(specifically, the /MCS2 output) is used to give the
software a way to hardware Reset the ISCC, IUSC, and
(M)USC. This allows a customer’s program to operate as
if it were in a target system starting from Reset, including
the initial write to the Bus Configuration Register (BCR).
The 80186’s two integrated DMA channels can be used for
any two of the four or six serial data streams in the B side
of the (E)SCC and the (M)USC. The “DMA EPLD” derives
requests for the 80186’s two DMA channels from six
inputs, two each for (E)SCC channel B and the one or two
channels in the (M)USC. It asserts DREQ0 or DREQ1
(High) if any of the inputs for that channel is low, and the
80186 is not performing an Interrupt Acknowledge cycle.
Jumper blocks J22, J23, J24, and J29 control the
assignment of the 80186’s internal DMA controllers,
including provision for a clipped Tx request that is needed
if a standard SCC is installed in place of the ESCC. The
various possibilities are summarized in Table 1.
Table 1. 80186 DMA Jumper Connections
To enable the following to use 80186 DMA Channel 0:
(E)SCC B Rx
MUSC Rx or USC A Rx
MUSC Tx or USC A Tx
USC B Rx
USC B Tx
Install this jumper:
J23-1 to J23-2
J22-1 to J22-2
J22-4 to J22-2
J29-1 to J29-2
J29-4 to J29-2
To enable the following to use 80186 DMA Channel 1:
ESCC B Tx
(E)SCC B Tx w/early release
MUSC Rx or USC A Rx
MUSC Tx or USC A Tx
USC B Rx
USC B Tx
Install this Jumper:
J24-1 to J24-3
J24-1 to J24-2
J22-1 to J22-3
J22-4 to J22-3
J29-1 to J29-3
J29-4 to J29-3
If more than one channel among the ESCC B and (M)USC
are enabled for one of the 80186’s internal DMA channels,
software must ensure that only one of the enabled devices
makes requests during a given block transfer. This can be
done by leaving an entire Receiver or Transmitter idle or
disabled, or by programming the device so that the DMA
request is not output on the pin.
The ISCC and IUSC handle their own DMA transfers via
the 80186’s HOLD/HLDA facility.
Note: Either a Z16C33 MUSC or a Z16C30 USC can be
installed in socket U5. If this is done, references to the
(M)USC herein after may mean the USC as a whole or just
its channel A; which one should be clear from the context.
The inputs and outputs associated with the processor’s
integrated counter/timer facility are brought to the pin
header labelled J26 so that they can be used in
applications (Table 2).
Table 2. Counter/Timer Signal Locations
J26 pin
1
2
3
4
5
6
Signal
Timer In 1
Timer Out 1
Timer In 0
Timer Out 0
N/C
Ground
The 80186’s integrated interrupt controller is largely
bypassed in favor of the traditional Zilogical interrupt
daisy-chain structure.
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