Z85233 Datasheet, PDF (199/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

Application Note
The Zilog Datacom Family with the 80186 CPU
(E)SCC
Socket U2 can be configured for either an ESCC or SCC,
and for versions thereof that use either multiplexed or non-
multiplexed address and data. Jumper blocks J20 and J21
select certain signals accordingly. For a part with
multiplexed addresses and data (80x30), jumper J20-J1 to
J20-J2 and leave J20-J3 open, and jumper J21-J1 to J21-
J2 and J21-J4 to J21-J5, leaving J21-J3 and J21-J6 open.
With such a part, software can directly address the
(E)SCC’s registers, and need not concern itself with
writing register addresses to Write Register 0 (WR0).
For a part having a non-multiplexed bus (85x30), jumper
J20-J2 to J20-J3, J21-J2 to J21-J3, and J21-J5 to J21-J6,
leaving J20-J1, J21-J1, and J21-J4 open. In this case,
software must handle the (E)SCC by writing register
addresses into its WR0 in order to access any register
other than WR0, RR0, or the data registers.
Channels A and B can be handled on a polled or interrupt-
driven basis. Channel A of the (E)SCC is suggested for
connecting the user’s PC or terminal for use with the
Debug Monitor included in this evaluation kit. Channel B
(but not A) can be handled on a DMA basis using the
80186’s internal DMA channels, or on a polled or interrupt
driven basis.
Jumper block J23 allows channel B’s /W//REQB output to
be used for either a Wait function or a Receive DMA
Request function. To use the output for Wait, jumper J23-
J2 to J23-J3 and leave J23-J1 open. The Wait function is
only significant if the software wants to delay completion of
a Read from the (E)SCC’s Receive Data register until data
is available, and/or if it wants to delay completion of a Write
to the Transmit Data register until the previously-written
character has been transferred to the Transmit Shift
register. These modes are alternatives to checking the
corresponding status flags and can be used to achieve
operating speeds higher than those possible with such
traditional polling, although not as fast as the speeds
possible with a DMA approach.
To use the /W//REQB output as a Receive DMA Request,
jumper J23-J1 to J23-J2 and leave J23-J3 open.
Jumper block J24 determines how channel B’s /DTR/
/REQB output is used. To use this output for the Data
Terminal Ready function, jumper J24-J3 to J24-J4 and
leave J24-J1 and J24-J2 open. To use this output directly
as a Transmit DMA Request (using the ESCC’s early-
release capability), jumper J24-J1 to J24-J3 and leave
J24-J2 and J24-J4 open. To drive the Transmit DMA
Request with a clipped version of this signal that is forced
High earlier than a standard SCC drives it High, jumper
J24-J1 to J24-J2 and leave J24-J3 and J24-J4 open.
The “SCC EPLD” handles the (E)SCC’s signalling
requirements. Among other things, this EPLD configures
the (E)SCC socket’s pins 35 and 36 for either a
multiplexed or non-multiplexed part, based on whether J20
is jumpered to connect the 80186 ALE signal to one of its
input pins. If the device detects high-going pulses on this
input, it drives corresponding low-going Address Strobe
pulses onto (E)SCC pin 35 and drives low-going Data
Strobe pulses onto (E)SCC pin 36.
If the SCC EPLD’s pin 9 stays at Ground, the part drives
Read strobes onto pin 36 and drives delayed Write strobes
onto pin 35, for a non-multiplexed 85x30 device.
While the ESCC’s relaxed timing capability allows the
80186’s /WR output to be connected directly to the /WR
input of a non-multiplexed ESCC, the SCC EPLD delays
start of an SCC’s write cycle until write data is valid, even
though this is not necessary for an ESCC.
The SCC EPLD also generates the clipped-DMA-request
signal mentioned in connection with J24, and logically ORs
Reset onto pins 35 and 36. The device also tracks the two
IACK cycles provided by the 80186 for each Interrupt
Acknowledge cycle. For a multiplexed address/data port, it
drives the address strobe (only) on the first cycle, and it
provides the /RD or /DS pulse needed by the (E)SCC
(only) on the second cycle. The “DMA EPLD” provides the
INTACK signal needed by the (E)SCC.
The (E)SCC is only accessible at even addresses. For a
non-multiplexed part (85x30), the following four register
locations are repeated throughout the even addresses
from (PBA) through (PBA)+126:
(PBA), (PBA)+8,... (PBA)+120
(PBA)+2, +10,... (PBA)+122
(PBA)+4, +12, ... (PBA)+124
(PBA)+6, +14, ... (PBA)+126
Channel B Command/Status register
Channel B Data register
Channel A Command/Status register
Channel A Data register
6-64
UM010901-0601