Z85233 Datasheet, PDF (59/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
Interfacing the SCC/ESCC
2.5 BLOCK/DMA TRANSFER (Continued)
Once the FIFO is locked, it allows the checking of the Re-
ceive Error FIFO (RR1) to find the cause of the error. Lock-
ing the data FIFO, therefore, stops the error status from
popping out of the Receive Error FIFO. Also, since the
DMA request becomes inactive, the interrupt (Special
Condition) is serviced.
Once the FIFO is unlocked by the Error Reset command,
/REQ again follows the state of the receive buffer.
In the case of the Z80X30, /REQ goes High in response to
the falling edge of /DS, but only if the appropriate receive
buffer in the SCC is accessed (Figure 2-33). In the case of
the Z85X30, /REQ goes High in response to the falling
edge of /RD, but only when the appropriate receive buffer
in the SCC is accessed (Figure 2-34).
/AS
AD7-AD0
WR8
Receive Data
/DS
PCLK
/REQ
/RD
D7- D0
PCLK
/REQ
Figure 2-33. Z80X30 Receive Request Release
Receive Data
Figure 2-34. Z85X30 Receive Request Release
2-40
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