Z85233 Datasheet, PDF (234/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

Application Note
Serial Communication Controller (SCC^™): SDLC Mode of Operation
Notes on Figure 3:
10. This interrupt is EOF (End of Frame), a Special
1. The receiver is usually in hunt mode when waiting for
Condition interrupt. This will not occur until the DMA
a frame. When the opening flag is received, an
External/Status Interrupt is generated, indicating the
1 ^{has read the 2nd CRC byte from the Receive Buffer.}
When it occurs, the Receive Buffer is locked and no
change from hunt mode to sync mode.
more DMA requests can be generated until the
Receive Buffer is unlocked by issuing the Error Reset
2. The /SYNC output follows the state of the sync register
command. Before issuing this command, all of the
comparison output. The comparison is done on a bit
status bits required (e.g., the CRC error status) must
by bit basis, so the /SYNC pin is only active for one bit-
be read, and the last two bytes read by the DMA
time. /SYNC goes active one bit-time after the last bit
discarded. The enable interrupt on next Receive
of the sync character is sampled at the RxD pin.
Character command must be sent to the SCC so that
3. A Receive Character Available Interrupt is generated
11 bit-times after the last bit of the character is
sampled at the RxD pin. In this mode, enable the DMA
on this interrupt. This interrupt is for data 81H.
the next character (i.e., the First Character of the next
frame) will produce an interrupt. If this is not done, the
character will generate a DMA request, not an
interrupt.
4. If SCC’s DMA request function has been enabled,
/REQ becomes active here.
5. DMA request for data 42H.
Should a Special Condition occur within the data
stream (i.e., for a condition other than EOF) the /INT
pin will not go active until the character with the
Special Condition has been read by the DMA.
6. DMA request for data 0FFH.
7. DMA request for data 42H.
8. DMA request for the first CRC byte. The SCC treats
the CRC as data, since the SCC does not yet
distinguish a difference between CRC and data!
9. DMA request for the second CRC byte. The closing
flag is recognized two bit-times before the second
CRC byte is completely assembled in the Receive
Shift Register. As soon as it is transferred to the
Receive Buffer, it generates a DMA request.
11. DMA request for 2nd CRC bytes. This occurs when
the EOF interrupt service routine has not disabled the
DMA function of the SCC, and did not read the data
after unlocking the buffer by issuing an Error Reset
command.
12. External/Status Interrupt for the Sync/Hunt change.
This occurs when the SCC recognizes an Abort
(Marking line) and forces the receiver into hunt mode.
The SCC can be programmed so that the Abort itself
generates an interrupt if required. If flag idle was set,
this interrupt would not occur.
UM010901-0601
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