Z85233 Datasheet, PDF (47/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
Interfacing the SCC/ESCC
2.4 INTERFACE PROGRAMMING (Continued)
2.4.8.3 Transmit Interrupt and Tx Underrun/EOM bit in
synchronous modes
As described in the section above, the behavior of the
NMOS/CMOS version and the ESCC is slightly different,
particularly at the end of packet sending. On the
NMOS/CMOS version, the data has higher priority over
CRC data; writing data before this interrupt would
terminate the packet illegally. In this case, the CRC byte(s)
are replaced with a Flag or Sync pattern, followed by the
data written. On the ESCC, the CRC has priority over the
data. That means after the reception of the Underrun/EOM
(End Of Message) interrupt, it accepts the data for the next
packet without collapsing the packet. On the ESCC, if data
was written during the time period described above, the
TBE bit (bit D2 of RR0) will not be set even if the second
TxIP is guaranteed to set when the flag/sync pattern was
loaded into the Transmit Shift Register, as mentioned
above (Figures 2-17 and 18). Hence, on the ESCC, there
is no need to wait for the second TxIP bit to set before
writing data for the next packet and reducing the overhead.
TBE (RR0, D2)
Last Data -1
Last Data
CRC1
CRC2
Flag
Can not write data
Tx Underrun /EOM
Indicating CRC get loaded
TxIP
Reset Tx Underrun/EOM command
If TxIP Reset Command
NOT Issued
TxIP Reset Command
to Clear Interrupt
Indicating 1st byte of next packet
can be written this time
Figure 2-20. Operation of TBE, Tx Underrun/EOM and TxIP on NMOS/CMOS.
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