Z85233 Datasheet, PDF (84/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
Data Communication Modes
mode, the transmitter sync length may be six or eight bits, the data must be right-justified, with the unused bits being
as selected by bit D0 of WR10.
ignored except in the case of five bits per character. When
4 ^{the five bits per character option is selected, the data must}
Monosync and Bisync modes require clocking information _{be formatted before being written to the transmit buffer to}
to be transmitted along with the data either by a method of _{allow transmission of from one to five bits per character.}
encoding data that contains clocking information, or by a _{This formatting is shown in Table 4-2.}
modem that encodes or decodes clock information in the
modulation process. Refer to the Monosync message for- An additional bit, carrying parity information, may be auto-
mat shown in Figure 4-4.
matically appended to every transmitted character by set-
ting bit D0 of WR4 to 1. This parity bit is sent in addition to
The Bisync mode of operation is similar to the Monosync _{the number of bits specified in WR4 or by the data format.}
mode, except that two sync characters are provided in- _{If this bit is set to 1, the transmitter sends even parity; if set}
stead of one. Bisync attempts a more structured approach _{to 0, the transmitted parity is odd. Parity is not typically}
to synchronization through the use of special characters _{used in synchronous applications because the CRC pro-}
as message headers or trailers.
vides a more reliable method for detecting errors.
Character-oriented mode is selected by programming bits
D3 and D2 of WR4 with zeros. This selects Synchronous
mode, as opposed to Asynchronous mode, but this selec-
tion is further modified by bits 5 and 7 of WR4 as well as
bits 1 and 0 of WR10. During the sync character-oriented
modes, except in External Sync mode, the state of bits 7
and 6 of WR4 are always forced internally to zeros. In ex-
ternal sync mode, these two bits must be programmed with
zeros (Table 4-4.). The combination, other than 00 in Ex-
ternal Sync mode, puts the SCC in special synchronization
modes.
Table 4-4. Registers Used in Character-Oriented
Modes
Reg
WR4
WR6
WR7
WR10
Bit No
3 (=0)
2 (=0)
4 (=0)
5 (=0)
4 (=1)
5 (=0)
4 (=1)
5 (=1)
6 (=0)
7 (=0)
7-0
7-0
1
Description
select sync mode
select monosync mode
(8-bit sync character)
select bisync mode
(16-bit sync character)
select external sync mode
(external sync signal required)
select 1x clock mode
sync character (low byte)
sync character (high byte)
select sync character length
In character-oriented modes, a special bit pattern is used
to provide character synchronization. The SCC offers sev-
eral options to support Synchronous mode including vari-
ous sync generation and checking, CRC generation and
checking, as well as modem controls and a transmitter to
receiver synchronization function.
The number of bits per transmitted character is controlled
by D6 and D5 of WR5 plus the way the data is formatted
within the transmit buffer. The bits in WR5 select the option
of five, six, seven, or eight bits per character. In all cases,
Either of two CRC polynomials are used in Synchronous
modes, selected by bit D2 in WR5. If this bit is set to 1, the
CRC-16 polynomial is used and, if this bit is set to 0, the
CRC-CCITT polynomial is used. This bit controls the se-
lection for both the transmitter and receiver. The initial
state of the generator and checker is controlled by bit D7
of WR10. When this bit is set to 1, both the generator and
checker have an initial value of all ones; if this bit is set to
0, the initial values are all zeros.
The SCC does not automatically preset the CRC genera-
tor in byte Synchronous modes, so this must be done in
software. This is accomplished by issuing the Reset Tx
CRC Generator command, which is encoded in bits D7
and D6 of WR0. For proper results, this command is is-
sued while the transmitter is enabled and sending sync
characters.
If the CRC is to be used, the transmit CRC generator must
be enabled by setting bit D0 of WR5 to 1. This bit may also
be used to exclude certain characters from the CRC calcu-
lation. Sync characters (from sync registers) are automat-
ically excluded from the CRC calculation, and any charac-
ters written as data are excluded from the calculation by
using bit D0 of WR5. Internally, enabling or disabling the
CRC for a particular character happens at the same time
the character is loaded from the transmit data buffer (on
the ESCC, the Transmit FIFO) to the Transmit Shift regis-
ter. Thus, to exclude a character from the CRC calculation
bit, D0 of WR5 is set to 0 before the character is written to
the transmit buffer (on the ESCC, the Transmit FIFO).
ESCC:
Since the ESCC has a four-byte FIFO, if a character is
to be excluded from the CRC calculation, it is recom-
mended that only one byte be written to the ESCC at
that time. If WR7' D5 is reset, the transmit interrupt is
generated when the FIFO is completely empty. This
can be used as a signal to reset WR5 bit D0, and then
the character can be written to the Transmit FIFO. This
guarantees that the internal disable occurs when the
character moves from the buffer to the shift register.
UM010901-0601
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