Z85233 Datasheet, PDF (58/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
Interfacing the SCC/ESCC
In the Request mode, /REQ will follow the state of the the /REQ signal, which is active Low. When REQ on Re-
transmit buffer even though the transmitter is disabled. ceive is selected, but not yet enabled (WR1 D7=0), the
2 ^{Thus, if /REQ is enabled before the transmitter is enabled, /W//REQ pin is driven High. When the enable bit is set,}
the DMA may write data to the SCC before the transmitter /REQ goes Low if the Receive FIFO contains a character
is enabled. This does not cause a problem in Asynchro- at the time, or will remain High until a character enters the
nous mode, but may cause problems in Synchronous Receive FIFO. Note that the /REQ pin follows the state of
modes because the SCC sends data in preference to flags the Receive FIFO even though the receiver is disabled.
or sync characters. It may also complicate the CRC initial- Thus, if the receiver is disabled and /REQ is still enabled,
ization, which cannot be done until after the transmitter is the DMA transfers the previously received data correctly.
enabled. On the ESCC, this complication can be avoided In this mode, the /REQ pin directly follows the state of the
in SDLC mode by using the Automatic SDLC Opening Flag Receive FIFO with only one exception. /REQ goes Low
Transmission feature and Auto EOM reset feature which when a character enters the Receive FIFO and remains
also resets the transmit CRC. (See section 4.4.1.2 for de- Low until this character is removed from the Receive FIFO.
tails). Applications using other synchronous modes should
enable the transmitter before enabling the /REQ function. ^{The SCC generates only one falling edge on /REQ per}
character transfer requested (Figure 2-32). The one ex-
With only one exception, the /REQ pin directly follows the ception occurs in the case of a special receive condition in
state of the Transmit FIFO (for ESCC, as programmed by the Receive Interrupt on First Character or Special Condi-
WR7' D5) in this mode. The one exception occurs in syn- tion mode, or the Receive Interrupt on Special Condition
chronous modes at the end of a CRC transmission. At the Only mode. In these two interrupt modes, any receive
end of a CRC transmission, when the closing flag or sync character with a special receive condition is locked at the
character is loaded into the Transmit Shift Register, /REQ top of the FIFO until an Error Reset command is issued.
is pulsed High for one PCLK cycle. The DMA uses this fall- This character in the Receive FIFO would ordinarily cause
ing edge on /REQ to write the first character of the next additional DMA Requests after the first time it is read.
frame to the SCC.
However, the logic in the SCC guarantees only one falling
edge on /REQ by holding /REQ High from the time the
2.5.2.4 DMA Request On Receive
character with the special receive condition is read, and
The Request On Receive function is selected by setting D6 _{the FIFO locked, until after the Error Reset command has}
and D5 of WR1 to 1 and then enabling the function by set- _{been issued.}
ting D7 of WR1 to 1. In this mode, the /W//REQ pin carries
Rx Character
Available
FIFO
Empty
Character Available
Read Strobe
to FIFO
W/REQ
(=REQ)
Figure 2-32. DMA Receive Request Assertion
UM010901-0601
2-39