Z85233 Datasheet, PDF (243/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

Application Note
Using SCC with Z8000 in SDLC Protocol
SYSTEM INTERFACE (Continued)
Two Z8000 Development Modules containing SCCs are
connected as shown in Figure 4 and Figure 5. The
Transmit Data pin of one is connected to the Receive Data
pin of the other and vice versa. The Z8002 is used as a
host CPU for loading the modules; memories with software
routines.
Figure 4. Block Diagram of Two Z8000 CPUs
The Z8002 CPU can address either of the two bytes
contained in 16-bit words. The CPU uses an even address
(16 bits) to access the most significant byte of a word and
an odd address for the least significant byte of a word.
When the Z8002 CPU uses the lower half of the
Address/Data bus (AD7-AD0 the least significant byte) for
byte read and write transactions during I/O operations,
these transactions are performed between the CPU and
I/O ports located at odd I/O addresses. Since the SCC is
attached to the CPU on the lower half of the A/D bus, its
registers must appear to the CPU at odd I/O addresses. To
achieve this, the SCC can be programmed to select its
internal registers using lines AD5-AD1. This is done either
automatically with the Force Hardware Reset command in
WR9 or by sending a Select Shift Left Mode command to
WR0B in channel B of the SCC. For this application, the
SCC registers are located at I/O port address “Fexx”. The
Chip Select signal (/CSO) is derived by decoding I/O
address “FE” hex from lines AD15-AD8 of the controller.
To select the read/write registers automatically, the SCC
decodes lines AD5-AD1 in Shift Left mode. The register
map for the SCC is depicted in Table 1.
Address
(Hex)
FE01
FE03
FE05
FE07
FE09
FE0B
FE0D
FE0F
FE11
FE13
FE15
FE17
FE19
FE1B
FE1D
FE1F
FE21
FE23
FE25
FE27
FE29
FE2B
FE2D
FE2F
FE31
FE33
FE35
FE37
FE39
FE3B
FE3D
FE3F
Table 1. Register Map
Write
Register
WR0B
WR1B
WR2
WR3B
WR4B
WR5B
WR6B
WR7B
B DATA
WR9
WR10B
WR11B
WR12B
WR13B
WR14B
WR15B
WR0A
WR1A
WR2
WR3A
WR4A
WR5A
WR6A
WR7A
A DATA
WR9
WR10A
WR11A
WR12A
WR13A
WR14A
WR15A
Read
Register
RR0B
RR1B
RR2B
RR3B
B DATA
RR10B
RR12B
RR13B
RR15B
RR0A
RR1A
RR2A
RR3A
A DATA
RR10A
RR12A
RR13A
RR15A
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