Z85233 Datasheet, PDF (96/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
Data Communication Modes
near the end of the frame to allow the correct transmission Deeper Transmit FIFO: The ESCC has a four byte deep
of the CRC.
Transmit FIFO, where the NMOS/CMOS version has a
4 ^{one byte deep transmit buffer. To maximize the system’s}
In this paragraph the term “completely sent” means shifted _{performance, there are two modes of operation for the}
out of the Transmit Shift register, not shifted out of the zero _{transmit interrupt and DMA request, which are pro-}
inserter, which is an additional five bit times of delay. In _{grammed by bit D5 of WR7'.}
SDLC mode, if the transmitter is disabled during transmis-
sion of a character, that character will be “completely sent.” The ESCC sets WR7' bit D5 to 1 following a hardware or
This applies to both data and flags. However, if the trans- software reset. This is done to provide maximum compat-
mitter is disabled during the transmission of the CRC, the ibility with existing SCC designs. In this mode, the ESCC
16-bit transmission will be completed, but the remaining generates the transmit buffer empty interrupt and DMA
bits are from the Flag register rather than the remainder of transmit request when the Transmit FIFO is completely
the CRC.
empty. Interrupt driven systems can maximize efficiency
by writing four bytes for each entry into the Transmit Inter-
The initialization sequence for the transmitter in SDLC _{rupt Service Routine (TISR), filling the Transmit FIFO with-}
mode is:
out having to check any status bits. Since the TBE status
1. WR4 selects the mode.
bit is set if the entry location of the FIFO is empty, this bit
can be tested at any time if more data is written. Applica-
2. WR10 modifies it if necessary.
tions requiring software compatibility with the
NMOS/CMOS version can test the TBE bit in the TISR af-
3. WR7 programs the flag.
ter each data write to determine if more data can be writ-
ten. This allows a system with an ESCC to minimize the
4. WR3 and WR5 selects the various options.
number of transmit interrupts, but not overflow SCC sys-
tems. DMA driven systems originally designed for the SCC
At this point the other registers should be initialized as nec- can use this mode to reassert the DMA request for more
essary. When all of this is complete, the transmitter may be data after the first byte written to the FIFO is loaded to the
enabled by setting bit D3 of WR5 to 1. Now that the trans- Transmit Shift register. Consequently, any subsequent re-
mitter is enabled, the CRC generator may be initialized by assertion allows the DMA sufficient time to detect the High-
issuing the Reset Tx CRC Generator command in WR0. to-Low edge.
4.4.1.1 Modem Control signals related to SDLC
Transmit
There are two modem control signals associated with the
transmitter provided by the SCC. The /RTS pin is a simple
output that carries the inverted state of the RTS bit (D1) in
WR5. The /CTS pin is ordinarily a simple input to the CTS
bit in RR0. However, if Auto Enables mode is selected, this
pin becomes an enable for the transmitter. If Auto Enables
is on and the /CTS pin is High, the transmitter is disabled.
The transmitter is enabled if the /CTS pin is Low.
4.4.1.2 ESCC Enhancements for SDLC Transmit
The ESCC has the following enhancements available in
the SDLC mode of operation which can reduce CPU over-
head dramatically. These features are:
s Deeper Transmit FIFO (Four Bytes)
s CRC takes priority over the data
s Auto EOM Reset (WR7' bit D1)
s Auto Tx Flag (WR7' bit D0)
s Auto RTS Deactivation (WR7' bit D2)
s TxD pin forced High after closing flag in NRZI mode
If WR7' D5 is reset to 0, the transmit buffer empty interrupt
and DMA request are generated when the entry location of
the FIFO is empty. Therefore, if more than one byte is re-
quired to fill the entry location of the FIFO, the ESCC gen-
erates interrupts or DMA requests until the entry location
of the FIFO is filled. The transmit DMA request pin (either
/WAIT//REQ or /DTR//REQ) goes inactive after each data
transfer, then goes active again and, consequently, gener-
ates a High-to-Low edge for each byte. Edge triggered
DMA should be enabled before the transmit DMA function
is enabled in the ESCC to guarantee that the ESCC does
not generate the edge before the DMA is ready.
CRC takes priority over data: On the NMOS/CMOS
version, the data has higher priority over CRC data. Writ-
ing data before the Tx interrupt, after loading the closing
flag into the Transmit Shift register, terminates the packet
illegally. In this case, CRC byte(s) are replaced with Flag
or Sync patterns, followed by the data written. On the ES-
CC, CRC has priority over the data. Consequently, after
the Underrun/EOM (End of message) interrupt occurs,
the ESCC accepts the data for the next packet without
fear of collapsing the packet. On the ESCC, if data was
written during the time period described above, the TBE
bit (bit D2 of RR0) is NOT set; even if the 2nd TxIP is
guaranteed to set when the flag/sync pattern is loaded
into the Transmit Shift register (Section 2.4.8). For the
detailed timing on this, refer to Figures 2-17 and 2-18.
UM010901-0601
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