Z85233 Datasheet, PDF (169/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

Application Note
The Z180™ Interfaced with the SCC at MHZ
(Continued)
4.7 K Ω
/USRRAM
A7
A6
HCT10
/CSSCC
(To SCC Interface Logic)
Figure 9b. I/O Address Decoder for this Board
When expanding this board to enable other peripherals,
the decoded address A6/A7 is NANDed with USRIO to
produce the Chip Enable (CSSCC) output signal (HC10).
The SCC registers are assigned from address xxC0h to
xxC3h; with image, they occupy xxC0h to xxFFh. To add
wait states during I/O transactions, use the Z180 on-chip
wait state generator instead of external hardware logic.
If there is a Z80 PIO on board in a Z-mode of operation
(that is, clear /M1E in OMCR register to zero) and after
enabling a Z80 PIO interrupt, zero is written to M1TE in the
OMCR register. Without a zero, there is no interrupt from
the Z80 PIO. The Z80 PIO requires /M1 to activate an
interrupt circuit after enabling interrupt by software.
Z180 TO SCC INTERFACE
The following subsections discuss the various parameters
between the Z180/SCC interface: CPU hardware, I/O
operation (read/write), SCC interrupts, Z80 interrupt daisy-
chain operation, SCC interrupt daisy-chain operation, I/O
cycles.
CPU Hardware Interfacing
The hardware interface has three basic groups of signals:
Data bus, system control, and interrupt control. For more
detailed signal information, refer to Zilog’s Technical
Manuals, and Product Specifications for each device.
Data Bus Signals
D7-D0. Data bus (Bidirectional, tri-state). This bus
transfers data between the Z180 and SCC.
System Control Signals
A//B, C//D. Register select signals (Input). These lines
select the registers.
/CE. Chip enable (Input, active low). /CE selects the
proper peripheral for programming. /CE is gated with
/IORQ or /MREQ to prevent false chip selects during other
machine cycles.
/RD+. Read (input, active low). /RD activates the chip-
read circuitry and gates data from the chip onto the data
bus.
/WR+. Write (Input, active low). /WR strobes data from the
data bus into the peripheral.
Chip reset occurs when /RD and /WR are active
simultaneously.
Interrupt Control
/INTACK. Interrupt Acknowledge (input, active low). This
signal shows an Interrupt Acknowledge cycle which
combines with /RD to gate the interrupt vector onto the
data bus.
/INT. Interrupt request (output, open-drain, active low).
IEI. Interrupt Enable In (input, active high).
IEO. Interrupt Enable Out (Output, active high).
These lines control the interrupt daisy chain for the
peripheral interrupt response.
SCC I/O Operation
The SCC generates internal control signals from /RD or
/WR. Since PCLK has no required phase relationship to
/RD or /WR, the circuitry generating these signals provides
time for meta stable conditions to disappear.
The SCC starts the different operating modes by
programming the internal registers. Accessing these
internal registers occurs during I/O Read and Write cycles,
described below.
Read Cycle Timing
Figure 10 illustrates the SCC Read cycle timing. All
register addresses and /INTACK are stable throughout the
cycle. The timing specification of SCC requires that the
/CE signal (and address) be stable when /RD is active.
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