Z85233 Datasheet, PDF (161/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

Application Note
The Z180™ Interfaced with the SCC at MHZ
INTERFACES
The following subsections explain the interfaces between
the:
s Z180 and Memory
s Z180 and I/O
s Z180 and SCC
Basic goals of this system design are:
s System clock up to 10 MHz
s Using the Z8018010VSC (Z180 10 MHz PLCC
package) to take advantage of 1M byte addressing
space and compactness (DIP versions’ addressing
range is half; 512K bytes)
s Using Z85C3010VSC (CMOS SCC 10 MHz PLCC
package)
s Minimum parts count
s Worst case design
s Using EPLD for glue wherever possible
s Expendability
The design method for EPLD is using TTLs (74HCT) and
then translating them into EPLD logic. This design uses
TTLs and EPLDs. With these goals in mind, the discussion
begins with the Z180-to-memory interface.
Z180 to Memory Interface
The memory access cycle timing of the Z180 is similar to
the Z80 CPU memory access cycle timing. The three
classifications are:
s Opcode fetch cycle (Figure 1)
s Memory read cycle (Figure 2)
s Memory write cycle (Figure 3)
Table 1 shows the Z180’s basic timing elements for the
opcode’s fetch/memory read/write cycle.
T1
T2
Tw
T3
T1
Ø
Address
/MREQ
/RD
Data
6
7
8
9
/M1
10
11
12
13
Read Data
15
11
16
14
Figure 1. Z180 Opcode Fetch Cycle Timing (One Wait State)
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