Z85233 Datasheet, PDF (293/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

Application Note
On-Chip Oscillator Design
PRACTICE: CIRCUIT ELEMENT AND LAY OUT CONSIDERATIONS (Continued)
Output Level. The signal at the amplifier output should
swing from ground to V_CC. This indicates there is adequate
gain in the amplifier. As the oscillator starts up, the signal
amplitude grows until clipping occurs, at which point, the
loop gain is effectively reduced to unity and constant
oscillation is achieved. A signal of less than 2.5 Vp-p is an
indication that low gain may be a problem. Either C1/C2
should be made smaller or a low R crystal should be used.
XTAL
2
64
CL
Z80180
20 mm
max
Signal Line
Layout Should
Avoid High
Lighted Areas
GND
3
CL
EXTAL
20 mm max
Clock Generator Circuit
Signals A B
(Parallel Traces
Must Be Avoided)
Signal C
2
64
Z80180
3
1
64
CLK
2
3
Z80180
Board Design Example
(Top View)
q To prevent induced noice, the crystal and load
capacitors should be physically located as
close to the LSI as possible.
q Signal lines should not run parallel to the clock
oscillator inputs. In particullar, the clock input
circuitry and the system clock output (pin 64)
should be separated as much as possible.
q ^{Vcc power lines should be separated from the}
clock oscillator input circuitry.
q Resistivity between XTAL or EXTAL and the
other pin should be greater than 10 MΩ
Figure 9. Circuit Board Design Rules
6-158
UM010901-0601