Z85233 Datasheet, PDF (214/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

APPLICATION NOTE
9
SCC IN BINARY
SYNCHRONOUS COMMUNICATIONS
9
INTRODUCTION
Zilog’s Z8030 Z-SCC Serial Communications Controller is
one of a family of components that are Z-BUS^® compatible
with the Z8000™ CPU. Combined with a Z8000 CPU (or
other existing 8- or 16-bit CPUs with nonmultiplexed buses
when using the Z8530 SCC), the Z-SCC forms an
integrated data communications controller that is more
cost effective and more compact than systems
incorporating UARTs, baud rate generators, and phase-
locked loops as separate entities.
The approach examined here implements a communications
controller in a Binary Synchronous mode of operation, with a
Z8002 CPU acting as controller for the Z-SCC.
One channel of the Z-SCC is used to communicate with
the remote station in Half Duplex mode at 9600
bits/second. To test this application, two Z8000
Development Modules are used. Both are loaded with the
same software routines for initialization and for
transmitting and receiving messages. The main program
of one module requests the transmit routine to send a
message of the length indicated in the ‘COUNT’
parameter. The other system receives the incoming data
stream, storing the message in its resident memory.
DATA TRANSFER MODES
The Z-SCC system interface supports the following data
transfer modes:
s Polled Mode. The CPU periodically polls the Z-SCC
status registers to determine the availability of a
received character, if a character is needed for
transmission, and if any errors have been detected.
s Interrupt Mode. The Z-SCC interrupts the CPU when
certain previously defined conditions are met.
s Block/DMA Mode. Using the Wait/Request (/W//REQ)
signal, the Z-SCC introduces extra wait cycles to
synchronize data transfer between a CPU or DMA
controller and the Z-SCC.
The example given here uses the block mode of data
transfer in its transmit and receive routines.
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