Z85233 Datasheet, PDF (181/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

Application Note
The Z180™ Interfaced with the SCC at MHZ
(Continued)
System Checkout
After completion of the board (PC board or wire wrapped
board, etc.), the following methods verify that the board is
working.
Software Considerations
Based on the previous discussion, it is necessary to
program the Z180 internal registers, as follows, before
system checkout:
s Z80 mode of operation - Clear /M1E bit in OMCR
register to zero (to provide expansion for Z80
peripherals).
s Z80 compatible mode - Clear IOC bit in OMCR register
to zero.
s Put one wait state in memory cycle, and no wait state for
I/O cycle DMCR register bits 7 and 6 to “1” and bits 5 and
4 to “0”.
SCC Read Cycle Proof
Read cycle checking is first because it is the simplest
operation. The SCC Read cycle is checked by reading the
bits in RR0. First, the SCC is hardware reset by
simultaneously pulling /RD and /WR LOW (The circuit
above includes the circuit for this). Then, reading out the
Read Register 0 returns:
D7-D0 = 01xxx100b
Bit D2, D6:1
Bit D7, D1, D0:0
Bit D5: Reflects /CTS pin
Bit D4: Reflects /SYNC
Bit D3: Reflects /DCD pin
Interrupt Acknowledge Cycle
Checking an Interrupt Acknowledge (/INTACK) cycle
consists of several steps. First, the SCC makes an
Interrupt Request (/INT) to the Z180. When the processor
is ready to service the interrupt, it shows an Interrupt
Acknowledge (/INTACK) cycle. The SCC then puts an 8-
bit vector on the bus and the Z180 uses that vector to get
the correct service routine. The following test checks the
simplest case.
First, load the Interrupt Vector Register (WR2) with a
vector, disable the Vector Interrupt Status (VIS) and
enable interrupts (IE=1, MIE=1 IEI=1). Disabling VIS
guarantees only one vector on the bus. The address of the
service routine corresponding to the 8-bit vector number
loads the Z180 vector table, and the Z180 is under
Interrupt Mode 2.
Because the user cannot set the SCC Interrupt Pending Bit
(IP), setting an interrupt sequence is difficult. An interrupt
is generated indirectly via the CTS pin by enabling the
following explanation.
Enable interrupt by /CTS (WR15, 20h), External/Status
Interrupt Enable (WR1, 01h), and Master Interrupt Enable
(WR9, 08h). Any change on the /CTS pin begins the
interrupt sequence. The interrupt is re-enabled by Reset
External/Status Interrupt (WR0, 10h) and Reset Highest
IUS (WR0, 38h).
A sample program of an SCC Interrupt Test is shown in
Table 12. The following programs in Tables 12, 13, and 14
assume that the 180 is correctly initialized. Table 12 uses
the Assembler for the Z80 CPU.
SCC Write Cycle Proof
Write cycle checking involves writing to a register and
reading back the results to the registers which return the
written value. The Time Constant registers (WR12 and
WR13) and External/Status Interrupt Enable register
(WR15) are on the SCC.
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UM010901-0601