Z85233 Datasheet, PDF (143/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

Application Note
Interfacing Z80^® CPUs to the Z8500 Peripheral Family
Z80B CPU TO Z8500A PERIPHERALS
No additional Wait states are necessary during I/O cycles,
although Wait states can be inserted to compensate for
any systems delays. Although the Z80B timing parameters
indicate a negative value for data valid prior to /WR, this is
a worse than “worst case” value. This parameter is based
upon the longest (worst case) delay for data available from
the falling edge of the CPU clock minus the shortest (best
case) delay for CPU clock High to /WR Low. The negative
value resulting from these two parameters does not occur
because the worst case of one parameter and best case of
the other do not occur within the same device. This
indicates that the value for data available prior to /WR will
always be greater than zero.
All setup and pulse width times for the Z8500A peripherals
are met by the standard Z80B timing. In determining the
interface necessary, the /CE signal to the Z8500A
peripherals is assumed to be the decoded address
qualified with /IORQ signal.
Figure 5 shows the minimum Z80B CPU to Z8500A
peripheral interface timing for I/O cycles. If additional Wait
states are needed, the same number of Wait states can be
inserted for both I/O Read and I/O Write cycles in order to
simplify interface logic. There are several ways to place
the Z80B CPU into a Wait condition (such as counters or
shift registers to count system clock pulses), depending
upon whether or not the user wants to place Wait states in
all I/O cycles, or only during Z8500A I/O cycles. Tables 6
and 7 list the Z8500A peripheral and Z80B CPU timing
parameters (respectively) of concern during the I/O cycles.
Tables 8 and 9 list the equations used in determining if
these parameters are satisfied. In generating these
equations and the values obtained from them, the required
number of Wait states was taken into account. The
reference numbers in Tables 6 and 7 refer to the timing
diagram of Figure 5.
Figure 5. Z80B CPU to Z8500A Peripheral Minimum I/O Cycle Timing
6-8
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