Z85233 Datasheet, PDF (200/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

Application Note
The Zilog Datacom Family with the 80186 CPU
For a multiplexed part (80 x 30), the Select Shift Left basic (E)SCC register map occurs twice in the even
command (D1-0=11) should be written to Channel B’s addresses from (PBA) through (PBA)+126:
WR0 before any other registers are accessed. Then the
8
(PBA), (PBA)+2, ... (PBA)+30
Channel B registers 0-15
(PBA)+32, +34, ... (PBA)+62
Channel A registers 0-15
(PBA)+64, +66, ... (PBA)+94
Channel B registers 0-15
(PBA)+96, +98, ... (PBA)+126
Channel A registers 0-15
The redundant addressing of the (E)SCC is used to control
a feature that can be used by software to allow the user to
interrupt software execution from his keyboard. If the
(E)SCC is read at an address with A6-A5=11 (for a
multiplexed part this means in the higher-addressed A
channel), a mode is set in which a low on the console
Received Data line (i.e., a Start bit on pin 3 of the J1
connector) causes a Non-Maskable Interrupt on the
80186. The mode is cleared by Reset, or when the (E)SCC
is read at an address with A6-A5=10 (on a multiplexed
part, in the higher-addressed B channel). The NMI handler
should do the latter fairly quickly to prevent subsequent
data bits on Received Data from causing further NMIs.
ISCC
Since the 80186 processor provides multiplexed
addresses and data, the ISCC is configured to use the
addresses on the AD lines. Therefore, software can
address the various ISCC registers directly, and need not
be concerned with writing register addresses into the
indirect address fields of the ISCC’s WR0 and CCAR.
Because the ISCC includes four DMA channels, its
Channel A and B Transmitters and Receivers can be
handled on a polled, interrupt-driven, and/or DMA basis, in
any mixture.
Since the ISCC can only be programmed as an 8-bit
device on the AD7-AD0 lines, it occupies only the even-
addressed bytes within its address range, (PBA)+128
through (PBA)+254.
The first write to this address range, after a Reset,
implicitly writes the ISCC’s Bus Configuration Register
(BCR). To match up with the rest of the board’s hardware,
this first write should be a byte write that stores the
hexadecimal value C6 in any even address in the first half
of the ISCC’s address range [(PBA)+128 through
(PBA)+190]. Details of this transaction are as follows:
s The High induced by a pull-up resistor on the ISCC’s A/B
input selects the WAIT protocol on the /WAIT//RDY pin,
which corresponds to how the 80186 works. (In
subsequent register accesses, the A/B selection is
taken from A5 of the multiplexed address.)
s A Low on the ISCC’s SCC//DMA input, which is
connected to A6, is required by the internal logic of the
ISCC. This is why the BCR write is restricted to the first
half of the ISCC’s address range.
s As with all transactions between the 80186 and ISCC,
the address must be even because the ISCC only
accepts slave-mode data on the AD7-AD0 pins.
s The MSB of the data (D7) is 1 to enable the Byte Swap
feature, so that when the ISCC’s DMA controller is
reading transmit data from RAM, it takes alternate bytes
from AD7-AD0 and AD15-AD8.
s D6 of the data is 1 so that when the ISCC’s DMA
controller is reading transmit data from RAM, it takes
even-addressed bytes from D7-D0 and odd-addressed
bytes from D15-D8 (same function as the 80186).
s D2-D1 of the data are 11 to select double-pulsed mode
for the ISCC’s /INTACK input. Again, this is how the
80186 works.
s D0 of the data is 0 to select Shift Left Address mode so
that the ISCC subsequently takes register addressing
from the AD5-AD1 lines rather than from AD4-AD0. This
is because the 80186 is a 16-bit processor that locates
even-addressed bytes on AD7-AD0 and odd-addressed
bytes on AD15-AD8, but the ISCC only accepts slave-
mode writes on the AD7-AD0 pins.
UM010901-0601
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