Z85233 Datasheet, PDF (192/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

Application Note
The Z180™ Interfaced with the SCC at MHZ
First, this program (Table 14) initializes the SCC by:
DMAC1: For Tx data transfer: Mem to I/O, Source
address-increasing, Destination address - fixed. Edge
Async, X1 mode, 8-bit 1 stop, Non-parity.
sense mode: Interrupt on end of transfer.
Tx and Rx clock from BRG, and BRG set to
7
PCLK/4.Self Loopback
Now, start sending with DMA.
Then, it initializes 4K bytes of memory with a repeating
pattern beginning with 00h and increases by one to FFh
(uses this as Tx buffer area). Also, it begins another 4K
bytes of memory as a Rx buffer with all zeros. After
starting, DMA initialization follows:
DMAC0: For Rx data transfer: I/O to Mem, Source
address- fixed, Destination address-increasing. Edge
sense mode: Interrupt on end of transfer.
On completion of the transfer, the Z180 DMAC1 generates
an interrupt. Then, wait for the interrupt from DMAC0
which shows an end of receive. Now, compare received
data with sent data. If the transfer was successful (source
data matched with destination), 00h is left in the
accumulator. If not successful, 0FFh is left in the
accumulator.
This program example specifies a way to initialize the SCC
and the Z180 DMA.
CONCLUSION
This Application Note describes only one example of
implementation, but gives you an idea of how to design the
system using the Z180™ and SCC.
For further design assistance, a completed board together
with the Debug/Monitor program and the listed sample
program are available. If interested, please contact your
local Zilog sales office.
UM010901-0601
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