Z85233 Datasheet, PDF (121/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
Register Descriptions
5.1 INTRODUCTION (Continued)
5.2.12 Write Register 9 (Master Interrupt
Control)
WR9 is the Master Interrupt Control register and contains
the Reset command bits. Only one WR9 exists in the SCC
and is accessed from either channel. The Interrupt control
bits are programmed at the same time as the Reset
command, because these bits are only reset by a
hardware reset. Bit positions for WR9 are shown in Figure
5-11.
Write Register 9
D7 D6 D5 D4 D3 D2 D1 D0
0 0 No Reset
0 1 Channel Reset B
1 0 Channel Reset A
1 1 Force Hardware Reset
VIS
NV
DLC
MIE
Status High//Status Low
Software INTACK Enable
(Reserved on NMOS)
Figure 5-11. Write Register 9
Bit 7 and 6: Reset Command Bits
Together, these bits select one of the reset commands for
the SCC. Setting either of these bits to 1 disables both the
receiver and the transmitter in the corresponding channel;
forces TxD for that channel marking, forces the modem
control signals High in that channel, resets all IPs and IUSs
and disables all interrupts in that channel. Four extra PCLK
cycles must be allowed beyond the usual cycle time after
any of the reset commands is issued before any additional
commands or controls are written to the channel affected.
Null Command (00). This command has no effect. It is
used when a write to WR9 is necessary for some reason
other than an SCC Reset command.
Channel Reset B Command (01). Issuing this command
causes a channel reset to be performed on Channel B.
Channel Reset A Command (10). Issuing this command
causes a channel reset to be performed on Channel A.
Force Hardware Reset Command (11). The effects of
this command are identical to those of a hardware reset,
except that the Shift Right/Shift Left bit is not changed and
the MIE, Status High/Status Low and DLC bits take the
programmed values that accompany this command.
Bit 5: Software Interrupt Acknowledge control bit
If bit D5 is set, reading Read Register 2 (RR2) results in an
interrupt acknowledge cycle to be executed internally. Like
a hardware INTACK cycle, a software acknowledge caus-
es the INT pin to return High, the IEO pin to go Low, and
sets the IUS latch for the highest priority interrupt pending.
This bit is reserved on NMOS, and always writes as 0.
Bit 4: Status High//Status Low control bit
This bit controls which vector bits the SCC modifies to in-
dicate status. When set to 1, the SCC modifies bits V6, V5,
and V4 according to Table 5-6. When set to 0, the SCC
modifies bits V1, V2, and V3. This bit controls status in
both the vector returned during an interrupt acknowledge
cycle and the status in RR2B. This bit is reset by a hard-
ware reset.
Table 5-6. Interrupt Vector Modification
V3 V2 V1 Status High/Status Low =0
V4 V5 V6 Status High/Status Low =1
0
0
0 Ch B Transmit Buffer Empty
0
0
1 Ch B External/Status Change
0
1
0 Ch B Receive Char. Available
0
1
1 Ch B Special Receive Condition
1
0
0 Ch A Transmit Buffer Empty
1
0
1 Ch A External/Status Change
1
1
0 Ch A Receive Char. Available
1
1
1 Ch A Special Receive Condition
Bit 3: Master Interrupt Enable
This bit is set to 1 to globally enable interrupts, and cleared
to zero to disable interrupts. Clearing this bit to zero forces
the IEO pin to follow the state of the IEI pin unless there is
an IUS bit set in the SCC. No IUS bit is set after the MIE
bit is cleared to zero. This bit is reset by a hardware reset.
Bit 2: Disable Lower Chain control bit
The Disable Lower Chain bit is used by the CPU to control
the interrupt daisy chain. Setting this bit to 1 forces the IEO
pin Low, preventing lower priority devices on the daisy
chain from requesting interrupts. This bit is reset by a hard-
ware reset.
Bit 1: No Vector select bit
The No Vector bit controls whether or not the SCC re-
sponds to an interrupt acknowledge cycle. This is done by
placing a vector on the data bus if the SCC is the highest
priority device requesting an interrupt. If this bit is set, no
vector is returned; i.e., AD7-AD0 remains tri-stated during
an interrupt acknowledge cycle, even if the SCC is the
highest priority device requesting an interrupt.
5-14
UM010901-0601