Z85233 Datasheet, PDF (12/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
General Description
1.2 SCC’S CAPABILITIES
The NMOS version of the SCC is Zilog’s original device.
The design is based on the Z80 SIO architecture. If you are
familiar with the Z80 SIO, the SCC can be treated as an
SIO with support circuitry such as DPLL, BRG, etc. Its fea-
tures include:
s Two independent full-duplex channels
s Synchronous/Isosynchronous data rates:
– Up to 1/4 of the PCLK using external clock source.
Up to 5 Mbits/sec at 20 MHz PCLK (ESCC)
Up to 4 Mbits/sec at 16 MHz PCLK (CMOS)
Up to 2 MBits/sec at 8 MHz PCLK (NMOS)
– Up to 1/8 of the PCLK (up to 1/16 on NMOS) using
FM encoding with DPLL
– Up to 1/16 of the PCLK (up to 1/32 on NMOS)
using NRZI encoding with DPLL
s Asynchronous Capabilities
– 5, 6, 7 or 8 bits/character (capable of handling 4
bits/character or less.)
– 1, 1.5, or 2 stop bits
– Odd or even parity
– Times 1, 16, 32 or 64 clock modes
– Break generation and detection
– Parity, overrun and framing error detection
s Byte oriented synchronous capabilities:
– Internal or external character synchronization
– One or two sync characters (6 or 8 bits/sync
character) in separate registers
– Automatic Cyclic Redundancy Check (CRC)
generation/detection
s SDLC/HDLC capabilities:
– Abort sequence generation and checking
– Automatic zero insertion and detection
– Automatic flag insertion between messages
– Address field recognition
– I-field residue handling
– CRC generation/detection
– SDLC loop mode with EOP recognition/loop entry
and exit
s Receiver FIFO
ESCC: 8 bytes deep
NMOS/CMOS: 3 bytes deep
s Transmitter FIFO
ESCC: 4 bytes deep
NMOS/CMOS: 1 byte deep
s NRZ, NRZI or FM encoding/decoding. Manchester code
decoding (encoding with external logic).
s Baud Rate Generator in each channel
s Digital Phase Locked Loop (DPLL) for clock recovery
s Crystal oscillator
The CMOS version of the SCC is 100% plug in compatible
to the NMOS versions of the device, while providing the
following additional features:
s Status FIFO
s Software interrupt acknowledge feature
s Enhanced timing specifications
s Faster system clock speed
s Designed in Zilog’s Superintegration^™ core format
s When the DPLL clock source is external, it can be up to
2x the PCLK, where NMOS allows up to PCLK (32.3
MHz max with 16/20 MHz version).
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