Z85233 Datasheet, PDF (91/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
Data Communication Modes
4.3 BYTE-ORIENTED SYNCHRONOUS MODE (Continued)
Table 4-7. Enabling and Disabling CRC
A
B
C
D
E
F
G
H
(Sync) (Data1) (Data2) (Data3) (CRC1) (CRC2) (Data) (Data)
Note: No CRC Calculation on "D"
Stage
Direction of Data
Shift
Receive Delay
Coming into SCC Register Data FIFO Register
CRC
1
HGFEDCB
d
HGFEDC
A
d
2
HGFEDC
B
CPU Read
B
d
CPU Enables CR
3
HGFED
C
B
e
CPU Read
C
HGFE
D
C
e
CPU Read
D*
CPU Disables CR
4
HGF
E
D
d
CPU Read
E
CPU Enables CR
HG
F
E
e
CPU Read
F
5
H
G
F
e
CPU Reads & Disca
G
H
G
e
Read RR1 D
H
Read H & Disca
H
Legend:
* Usually D is a end-of-message character indicator.
† The status is latched on the Error FIFO for each received byte. In the calculation of F,
the CRC error flag in the Error FIFO will be 0 for an error free message.
d = disabled
e = enabled
ABCDEFGH
A = SYNC
B - F = Data with E = CRC1 and F = CRC2
G and H are arbitrary data (Pad Character)
Notes
CRC Calc on B
CRC Calc on C
CRC Calc is
Disabled on D
CRC Calc on E
CRC Calc on F
CRC Calc on F
Result latched in
Error FIFO †
4-16
UM010901-0601