Z85233 Datasheet, PDF (4/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
Table of Contents
Chapter 3. SCC/ESCC Ancillary Support Circuitry
3.1 Introduction .................................................................................................................................... 3-1
3.2 Baud Rate Generator ..................................................................................................................... 3-1
3.3 Data Encoding/Decoding ............................................................................................................... 3-4
3.4 DPLL Digital Phase-Locked Loop .................................................................................................. 3-7
3.4.1 DPLL Operation in the NRZI Mode .................................................................................. 3-8
3.4.2 DPLL Operation in the FM Modes .................................................................................... 3-9
3.4.3 DPLL Operation in the Manchester Mode ...................................................................... 3-10
3.4.4 Transmit Clock Counter (ESCC only) ............................................................................. 3-10
3.5 Clock Selection ........................................................................................................................... 3-11
3.6 Crystal Oscillator ......................................................................................................................... 3-14
Chapter 4. Data Communication Modes
4.1 Introduction .................................................................................................................................... 4-1
4.1.1 Transmit Data Path Description ....................................................................................... 4-1
4.1.2 Receive Data Path Description ....................................................................................... 4-2
4.2 Asynchronous Mode ...................................................................................................................... 4-3
4.2.1 Asynchronous Transmit ................................................................................................... 4-4
4.2.2 Asynchronous Receive .................................................................................................... 4-6
4.2.3 Asynchronous Initialization ............................................................................................... 4-7
4.3 Byte-Oriented Synchronous Mode ................................................................................................. 4-8
4.3.1 Byte-Oriented Synchronous Transmit .............................................................................. 4-8
4.3.2 Byte-Oriented Synchronous Receive ............................................................................. 4-10
4.3.3 Transmitter/Receiver Synchronization ........................................................................... 4-17
4.4 Bit-Oriented Synchronous (SDLC/HDLC) Mode .......................................................................... 4-18
4.4.1 SDLC Transmit ............................................................................................................... 4-19
4.4.2 SDLC Receive ................................................................................................................ 4-22
4.4.3 SDLC Frame Status FIFO .............................................................................................. 4-27
4.4.4 SDLC Loop Mode ........................................................................................................... 4-30
Chapter 5. Register Descriptions
5.1 Introduction .................................................................................................................................... 5-1
5.2 Write Registers .............................................................................................................................. 5-2
5.2.1 Write Register 0 (Command Register) ............................................................................. 5-2
5.2.2 Write Register 1 (Transmit/Receive Interrupt and Data Transfer Mode Definition) .......... 5-4
5.2.3 Write Register 2 (Interrupt Vector) ................................................................................... 5-7
5.2.4 Write Register 3 (Receive Parameters and Control) ........................................................ 5-7
5.2.5 Write Register 4 (Transmit/Receive Miscellaneous Parameters and Modes) .................. 5-8
5.2.6 Write Register 5 (Transmit Parameters and Controls) ..................................................... 5-9
5.2.7 Write Register 6 (Sync Characters or SDLC Address Field) .......................................... 5-10
5.2.8 Write Register 7 (Sync Character or SDLC Flag) ........................................................... 5-11
5.2.9 Write Register 7 Prime (ESCC only) .............................................................................. 5-12
5.2.10 Write Register 7 Prime (85C30 only) .............................................................................. 5-13
5.2.11 Write Register 8 (Transmit Buffer) .................................................................................. 5-13
5.2.12 Write Register 9 (Master Interrupt Control) .................................................................... 5-14
5.2.13 Write Register 10 (Miscellaneous Transmitter/Receiver Control Bits) ........................... 5-15
5.2.14 Write Register 11 (Clock Mode Control) ......................................................................... 5-17
5.2.15 Write Register 12 (Lower Byte of Baud Rate Generator Time Constant) ....................... 5-18
5.2.16 Write Register 13 (Upper Byte of Baud Rate Generator Time Constant) ....................... 5-19
5.2.17 Write Register 14 (Miscellaneous Control Bits) .............................................................. 5-19
5.2.18 Write Register 15 (External/Status Interrupt Control) ..................................................... 5-20
5.3 Read Registers ............................................................................................................................ 5-21
5.3.1 Read Register 0 (Transmit/Receive Buffer Status and External Status) ........................ 5-21
5.3.2 Read Register 1 ............................................................................................................. 5-23
5.3.3 Read Register 2 ............................................................................................................. 5-24
5.3.4 Read Register 3 ............................................................................................................. 5-25
5.3.5 Read Register 4 (ESCC and 85C30 Only) ..................................................................... 5-25
5.3.6 Read Register 5 (ESCC and 85C30 Only) ..................................................................... 5-25
UM010901-0601
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