Z85233 Datasheet, PDF (24/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
Interfacing the SCC/ESCC
The Z80X30 samples the state of /INTACK on the rising Shift Right/Shift Left bit in the Channel B WR0 controls
edge of /AS, and AC parameters #7 and #8 specify the set- which bits are decoded to form the register address. It is
2 ^{up and hold-time requirements. Between the rising edge of placed in this register to simplify programming when the}
/AS and the falling edge of /DS, the internal and external current state of the Shift Right/Shift Left bit is not known.
daisy chains settle (AC parameter #29). A system with no
external daisy chain should provide the time specified in ^{A hardware reset forces Shift Left mode where the address}
spec #29 to settle the interrupt daisy-chain priority internal ^{is decoded from AD5-AD1. In Shift Right mode, the ad-}
to the SCC. Systems using an external daisy chain should ^{dress is decoded from AD4-AD0. The Shift Right/Shift Left}
refer to Note 5 referenced in the Z80X30 Read/Write & In- ^{bit is written via a command to make the software writing}
terrupt Acknowledge Timing for the time required to settle ^{to WR0 independent of the state of the Shift Right/Shift}
the daisy chain.
Left bit.
Note: /INTACK is sampled on the rising edge of /AS. If it
does not meet the setup time to the first rising edge of /AS
of the interrupt acknowledge cycle, it is latched on the next
rising edge of /AS. Therefore, if /INTACK is asynchronous
to /AS, it may be necessary to add a PCLK cycle to the cal-
culation for /INTACK to /RD delay time.
If there is an interrupt pending in the SCC, and IEI is High
when /DS falls, the acknowledge cycle was intended for
the SCC. This being the case, the Z80X30 sets the Inter-
rupt-Under-Service (IUS) latch for the highest priority
pending interrupt, as well as placing an interrupt vector on
AD7-AD0. The placing of a vector on the bus can be dis-
abled by setting WR9, D1=1. The /INT pin also goes inac-
tive in response to the falling edge of /DS. Note that there
should be only one /DS per acknowledge cycle. Another
important fact is that the IP bits in the Z80X30 are updated
by /AS, which may delay interrupt requests if the processor
does not supply /AS strobes during the time between ac-
cesses of the Z80X30.
2.2.4 Z80X30 Register Access
The registers in the Z80X30 are addressed via the address
on AD7-AD0 and are latched by the rising edge of /AS. The
While in the Shift Left mode, the register address is
placed on AD4-AD1 and the Channel Select bit, A/B, is
decoded from AD5. The register map for this case is
shown in Table 2-1. In Shift Right mode, the register ad-
dress is again placed on AD4-AD1 but the channel select
A/B is decoded from AD0. The register map for this case
is shown in Table 2-2.
Because the Z80X30 does not contain 16 read registers,
the decoding of the read registers is not complete; this is
indicated in Table 2-1 and Table 2-2 by parentheses
around the register name. These addresses may also be
used to access the read registers. Also, note that the
Z80X30 contains only one WR2 and WR9; these registers
may be written from either channel.
Shift Left Mode is used when Channel A and B are to be
programmed differently. This allows the software to se-
quence through the registers of one channel at a time. The
Shift Right Mode is used when the channels are pro-
grammed the same. By incrementing the address, the user
can program the same data value into both the Channel A
and Channel B register.
UM010901-0601
2-5