Z85233 Datasheet, PDF (45/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
Interfacing the SCC/ESCC
2.4 INTERFACE PROGRAMMING (Continued)
bit D5 nor the transmit interrupt status, and will respond
exactly the same way as mentioned above. Figure 2-17 il-
lustrates when the TBE bit will become set.
Note: When WR7' D5=0. only one byte is written to the
FIFO at a time, when there are three or fewer bytes in
FIFO. Thus, for the ESCC multiple interrupts are generat-
ed to fill the FIFO. To avoid multiple interrupts, one can poll
the TBE bit (RR0 D2) after writing each byte.
While transmit interrupts are enabled, the ESCC sets the
TxIP when the transmit buffer reaches the condition pro-
grammed in WR7' bit D5. This means that the transmit
buffer must have been written to before the TxIP is set.
Thus, when transmit interrupts are first enabled, the trans-
mit IP is not set until the programmed interrupting condition
is met.
The TxIP is reset either by writing data to the transmit buff-
er or by issuing the Reset Tx Int Pending command in
WR0. Ordinarily, the response to a transmit interrupt is to
write more data to the ESCC; however, if there is no more
data to be transmitted at that time, it is the end of the
frame. The Reset Tx Int command is used to reset the TxIP
and clear the interrupt. For example, at the end of a frame
or block of data where the CRC is to be sent next, the Re-
set Tx Int Pending command should be issued after the
last byte of data has been written to the ESCC.
In synchronous modes, one other condition can cause the
TxIP to be set. This occurs at the end of a transmission af-
ter the CRC is sent. When the last bit of the CRC has
cleared the Transmit Shift Register and the flag or sync
character is loaded into the Transmit Shift Register, the
ESCC sets the TxIP. Data for the new frame or block to be
transmitted may be written at this time. In this particular
case, the Transmit Buffer Empty bit in RR0 and the TxIP
are set.
An enhancement to the ESCC from the NMOS/CMOS ver-
sion is that the CRC has priority over the data, where on
the NMOS/CMOS version data has priority over the CRS.
This means that on the ESCC the CRC bytes are guaran-
teed to be sent, even if the data for the next packet has
written before the second transmit interrupt, but after the
EOM/Underrun condition exists. This helps to increase the
system throughput because there is not waiting for the
second transmit interrupt. On the NMOS/CMOS version, if
the data is written while the CRC is sent, CRC byte(s) are
replaced with the flag/sync pattern followed by the data.
Another enhancement of the ESCC is that it latches the
transmit interrupt because the CRC is loaded into the
Transmit Shift Register even if the transmit interrupt, due
to the last data byte, is not yet reset. Therefore, the end of
a synchronous frame is guaranteed to generate two
transmit interrupts even if a Reset Tx Int Pending
command for the data created interrupt is issued after
(Time “A” in Figure 2-16) the CRC interrupt had occurred.
In this case, two reset Tx Int Pending commands are
required. The TxIP is latched if the EOM latch has been
reset before the end of the frame.
04
TxFIFO
03
04
02
03
01
Tx Shift Register
No Transmit Interrupt
TxIP=0
02
No Transmit Interrupt
TxIP=0
Transmit Interrupt
TxIP=1
Figure 2-16. Transmit Interrupt Status When WR7' D5=1 For ESCC
2-26
UM010901-06
01