Z85233 Datasheet, PDF (82/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
Data Communication Modes
receiver. That is, if Auto Enables is on and the /DCD pin is _{4.2.3 Asynchronous Initialization}
High, the receiver is disabled; while the /DCD pin is low,
the receiver is enabled.
Received characters are assembled, checked for errors,
The initialization sequence for Asynchronous mode is
shown in Table 4-3. All of the SCC’s registers should be re-
initialized after a channel or hardware reset. Also, WR4
4
and moved to the receive data FIFO (eight bytes on ESCC, ^{should be programmed first after a reset.}
three bytes on NMOS/CMOS). The user can program the
SCC to generate an interrupt to the CPU or to request a
data read from a DMA when data is received.
Table 4-3. Initialization Sequence
Asynchronous Mode
On the NMOS/CMOS version, it generates the Receive
Character Available interrupt and DMA Request on Re-
ceive (if enabled). The receive interrupt and DMA request
is generated when there is at least one character in the
FIFO. The Rx Character Available (RCA) bit is set if there
is at least one byte available.
The ESCC generates the receive character available inter-
rupt and DMA request on Receive (if enabled) and is de-
pendent on WR7' bit D3. If this bit is reset to 0 (this mode
is comparable to the NMOS/CMOS version), the receive
interrupt and DMA request is generated when there is at
least one character in the FIFO. If WR7' bit D3 is set to 1,
the receive interrupt and DMA request are generated
when there are four bytes available in the Receive FIFO.
Reg Bit No Description
WR9
6, 7 Hardware or channel Reset
WR4
WR3
3, 2 Select Async Mode and the number
of stop bits*
0, 1 Select parity*
6, 7 Select clock mode*
7, 6 Select number of receive bits per
character
WR5
5 Select Auto Enables Mode*
6, 5 Select number of bits/char for
transmitter
1 Select modem control (RTS)
Note:
* Initializes transmitter and receiver simultaneously.
The RCA bit in RR0 follows the state of WR7' D3. The RCA
bit is set if there is at least one byte available, regardless
of the status of WR7' bit D3.
At this point, the other registers should be initialized ac-
cording to the hardware design such as clocking,
I/O mode, etc. When this is completed, the transmitter is
This is the initialization sequence for the receiver in Asyn- ^{enabled by setting WR5 bit D3 to 1 and the receiver is en-}
chronous mode. First, WR4 selects the mode, then WR3 ^{abled by setting WR3 bit D0 to 1.}
and WR5 select the various options. At this point, the other
registers should be initialized as necessary. When all of
this is complete, the receiver may be enabled by setting bit
D0 of WR3 to 1.
See Section 2.4.7 “The Receive Interrupt” for more details
on receive interrupts.
UM010901-0601
4-7