Z85233 Datasheet, PDF (51/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
Interfacing the SCC/ESCC
2.4 INTERFACE PROGRAMMING (Continued)
Because the latches close on the current status, but give
no indication of change, the processor must maintain a
copy of RR0 in memory. When the SCC generates an Ex-
ternal/Status Interrupt, the processor should read RR0 and
determine which condition changed state and take appro-
priate action. The copy of RR0 in memory is then updated
and the Reset External/Status Interrupt command issued.
Care must be taken in writing the interrupt service routine
for the External/Status interrupts because it is possible for
more than one status condition to change state at the
same time. All of the latch bits in RR0 should be compared
to the copy of RR0 in memory. If none have changed and
the ZC interrupt is enabled, the Zero Count condition
caused the interrupt.
On the ESCC, the contents of RR0 are latched while read-
ing this register. The ESCC prevents the contents of RR0
from changing while the read cycle is active. On the
NMOS/CMOS version, it is possible for the status of RR0
to change while a read is in progress, so it is necessary to
read RR0 twice to detect changes that otherwise may be
missed. The contents of RR0 are latched on the falling
edge of /RD and are updated after the rising edge of /RD.
The operation of the individual enable bits in WR15 for
each of the six sources of External/Status interrupts is
identical, but subtle differences exist in the operation of
each source of interrupt. The six sources are Break/Abort,
Underrun/EOM, CTS, DCD, Sync/Hunt and Zero Count.
The Break/Abort, Underrun/EOM, and Zero Count condi-
tions are internal to the SCC, while Sync/Hunt may be in-
ternal or external, and CTS and DCD are purely external
signals. In the following discussions, each source is as-
sumed to be enabled so that the latches are present and
the External/Status interrupts are enabled as a whole. Re-
call that the External/Status IP is set while the latches are
closed and that the state of the signal is reflected immedi-
ately in RR0 if the latches are not present.
2.4.9.1 Break/Abort
The Break/Abort status is used in asynchronous and
SDLC modes, but is always 0 in synchronous modes other
than SDLC. In asynchronous modes, this bit is set when a
break sequence (null character plus framing error) is de-
tected in the receive data stream, and remains set as long
as 0s continue to be received. This bit is reset when a 1 is
received. A single null character is left in the Receive FIFO
each time that the break condition is terminated. This char-
acter should be read and discarded.
In SDLC mode, this bit is set by the detection of an abort se-
quence which is seven or more contiguous 1s in the receive
data stream. The bit is reset when a 0 is received. A re-
ceived abort forces the receiver into Hunt, which is also an
external/status condition. Though these two bits change
state at roughly the same time, one or two External/Status
Interrupts may be generated as a result. The Break/Abort bit
is unique in that both transitions are guaranteed to cause
the latches to close, even if another External/Status inter-
rupt is pending at the time these transitions occur. This
guarantees that a break or abort will be caught. This bit is
undetermined after reset.
2.4.9.2 Transmit Underrun/EOM
The Transmit Underrun/EOM bit is used in synchronous
modes to control the transmission of the CRC. This bit is
reset by issuing the Reset Transmit Underrun/EOM com-
mand in WR0. However, this transition does not cause the
latches to close; this occurs only when the bit is set. To in-
form the processor of this fact, the SCC sets this bit when
the CRC is loaded into the Transmit Shift Register. This bit
is also set if the processor issues the Send Abort com-
mand in WR0. This bit is always set in Asynchronous
mode.
ESCC:
The ESCC has been modified so that in SDLC mode
this interrupt indicates when more data can be written
to the Transmit FIFO. When this interrupt is used in
this way, the Automatic SDLC Flag Transmission fea-
ture must be enabled (WR7' D0=1). On the ESCC, the
Transmit Underrun/EOM interrupt can be used to sig-
nal when data for a subsequent frame can be written
to the Transmit FIFO which more easily supports the
transmission of back to back frames.
2.4.9.3 CTS/DCD
The CTS bit reports the state of the /CTS input, and the
DCD bit reports the status of the /DCD input. Both bits
latch on either input transition. In both cases, after the Re-
set External/Status Interrupt command is issued, if the
latches are closed, they remain closed if there is any odd
number of transitions on an input; they open if there is an
even number of transitions on the input.
2.4.9.4 Zero Count
The Zero Count bit is set when the counter in the baud rate
generator reaches a count of 0 and is reset when the
counter is reloaded. The latches are closed only when this
bit is set to 1. The status in RR0 always reflects the current
status. While the Zero count IE bit in WR15 is reset, this bit
is forced to 0.
2.4.9.5 Sync/Hunt
There are a variety of ways in which the Sync/Hunt may be
set and reset, depending on the SCC’s mode of operation.
In the Asynchronous mode this bit reports the state of the
/SYNC pin, latching on both input transitions. The same is
true of External Sync mode. However, if the crystal oscilla-
tor is enabled while in Asynchronous mode, this bit will be
forced to 0 and the latches will not be closed. Selecting the
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