Z85233 Datasheet, PDF (113/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
Register Descriptions
5.1 INTRODUCTION (Continued)
When programmed to 1, this bit allows the Wait/Request
function to follow the state of the receive buffer. Thus, de-
pending on the state of bit 6, the /W//REQ pin is active or
inactive in relation to the empty or full state of the receive
buffer.
The request function occurs only when the SCC is not se-
lected; e.g., if the internal request becomes active while
the SCC is in the middle of a read or write cycle, the exter-
nal request does not become active until the cycle is com-
plete. An active request output causes a DMA controller to
initiate a read or write operation. If the request on Transmit
mode is selected in either SDLC or Synchronous Mode,
the Request pin is pulsed Low for one PCLK cycle at the
end of CRC transmission to allow the immediate transmis-
sion of another block of data.
In the Wait On Receive mode, the /WAIT pin is active if the
CPU attempts to read SCC data that has not yet been re-
ceived. In the Wait On Transmit mode, the /WAIT pin is ac-
tive if the CPU attempts to write data when the transmit
buffer is still full. Both situations occur frequently when
block transfer instructions are used.
Bits 4 and 3: Receive Interrupt Modes
Receive Interrupts Disabled (00). This mode prevents
the receiver from requesting an interrupt. It is normally
used in a polled environment where either the status bits
in RR0 or the modified vector in RR2 (Channel B) are mon-
itored to initiate a service routine. Although the receiver in-
terrupts are disabled, a special condition can still provide a
unique vector status in RR2.
Receive Interrupt on First Character or Special Condi-
tion (01). The receiver requests an interrupt in this mode
on the first available character (or stored FIFO character)
or on a special condition. Sync characters, stripped from
the message stream, do not cause interrupts.
Special receive conditions are: receiver overrun, framing
error, end of frame, or parity error (if selected). If a special
receive condition occurs, the data containing the error is
stored in the Receive FIFO until an Error Reset command
is issued by the CPU.
This mode is usually selected when a Block Transfer mode
is used. In this interrupt mode, a pending special receive
condition remains set until either an error Reset command,
a channel or hardware reset, or until receive interrupts are
disabled.
The Receive Interrupt on First Character or Special Condi-
tion mode can be re-enabled by the Enable Rx Interrupt on
Next Character command in WR0.
ESCC:
See the description of WR7' on how this function can
be changed.
Interrupt on All Receive Characters or Special Condi-
tion (10). This mode allows an interrupt for every character
received (or character in the Receive FIFO) and provides
a unique vector when a special condition exists. The Re-
ceiver Overrun bit and the Parity Error bit in RR1 are two
special conditions that are latched. These two bits are re-
set by the Error Reset command. Receiver overrun is al-
ways a special receive condition, and parity can be pro-
grammed to be a special condition.
Data characters with special receive conditions are not
held in the Receive FIFO in the Interrupt On All Receive
Characters or Special Conditions Mode as they are in the
other receive interrupt modes.
Receive Interrupt on Special Condition (11). This mode
allows the receiver to interrupt only on characters with a
special receive condition. When an interrupt occurs, the
data containing the error is held in the Receive FIFO until
an Error Reset command is issued. When using this mode
in conjunction with a DMA, the DMA is initialized and en-
abled before any characters have been received by the
ESCC. This eliminates the time-critical section of code re-
quired in the Receive Interrupt on First Character or Spe-
cial Condition mode. Hence, all data can be transferred via
the DMA so that the CPU need not handle the first re-
ceived character as a special case. In SDLC mode, if the
SDLC Frame Status FIFO is enabled and an EOF is re-
ceived, an interrupt with vector for receive data available is
generated and the Receive FIFO is not locked.
Bit 2: Parity Is Special Condition
If this bit is set to 1, any received characters with parity not
matching the sense programmed in WR4 give rise to a
Special Receive Condition. If parity is disabled (WR4), this
bit is ignored. A special condition modifies the status of the
interrupt vector stored in WR2. During an interrupt ac-
knowledge cycle, this vector can be placed on the data
bus.
Bit 1: Transmitter Interrupt Enable
If this bit is set to 1, the transmitter requests an interrupt
whenever the transmit buffer becomes empty.
Bit 0: External/Status Master Interrupt Enable
This bit is the master enable for External/Status interrupts
including /DCD, /CTS, /SYNC pins, break, abort, the begin-
ning of CRC transmission when the Transmit/Under-
run/EOM latch is set, or when the counter in the baud rate
generator reaches 0. Write Register 15 contains the individ-
ual enable bits for each of these sources of External/Status
interrupts. This bit is reset by a channel or hardware reset.
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