Z85233 Datasheet, PDF (29/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
Interfacing the SCC/ESCC
2.3 Z85X30 INTERFACE TIMING
Two control signals, /RD and /WR, are used by the
Z85X30 to time bus transactions. In addition, four other
control signals, /CE, D//C, A//B and /INTACK, are used to
control the type of bus transaction that occurs. A bus trans-
action starts when the addresses on D//C and A//B are as-
serted before /RD or /WR fall (AC Spec #6 and #8). The
coincidence of /CE and /RD or /CE and /WR latches the
state of D//C and A//B and starts the internal operation.
The /INTACK signal must have been previously sampled
High by a rising edge of PCLK for a read or write cycle to
occur. In addition to sampling /INTACK, PCLK is used by
the interrupt section to set the IP bits.
The Z85X30 generates internal control signals in response
to a register access. Since /RD and /WR have no phase re-
lationship with PCLK, the circuitry generating these inter-
nal control signals provides time for metastable conditions
to disappear. This results in a recovery time related to
PCLK.
This recovery time applies only between transactions in-
volving the Z85X30, and any intervening transactions are
ignored. This recovery time is four PCLK cycles (AC Spec
#49), measured from the falling edge of /RD or /WR in the
case of a read or write of any register.
2.3.1 Z85X30 Read Cycle Timing
The read cycle timing for the Z85X30 is shown in
Figure 2-5. The address on A//B and D//C is latched by the
coincidence of /RD and /CE active. /CE must remain Low
and /INTACK must remain High throughout the cycle. The
Z85X30 bus drivers are enabled while /CE and /RD are
both Low. A read with D//C High does not disturb the state
of the pointers and a read cycle with D//C Low resets the
pointers to zero after the internal operation is complete
.
A//B, D//C
Address Valid
/INTACK
/CE
/RD
D7-D0
Data Valid
Figure 2-5. Z85X30 Read Cycle Timing
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