Z85233 Datasheet, PDF (78/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
Data Communication Modes
Incoming data is routed through one of several paths de- been received and the receiver is synchronized to that flag.
pending on the mode and character length. In Asynchro- If the seventh bit is a 1, an abort or an EOP (End Of Poll) is
4 ^{nous mode, serial data enters the 3-bit delay if a character recognized, depending upon the selection of either the nor-}
length of seven or eight bits is selected. If a character mal SDLC mode or SDLCLoop mode.
length of five or six bits is selected, data enters the receive
shift register directly.
Note: The insertion and deletion of the zero in the SDLC
data stream is transparent to the user, as it is done after
In Synchronous modes, the data path is determined by the the data is written to the Transmit FIFO and before data is
phase of the receive process currently in operation. A syn- read from the Receive FIFO. This feature of the
chronous receive operation begins with a hunt phase in SDLC/HDLC protocol is to prevent the inadvertent sending
which a bit pattern that matches the programmed sync of an ABORT sequence as part of the data stream. It is
characters (6-,8-, or 16-bit) is searched.
also valuable to applications using encoded data to insure
a sufficient number of edges on the line to keep a DPLL
The incoming data then passes through the Sync register _{synchronized on a receive data stream.}
and is compared to a sync character stored in WR6 or
WR7 (depending on which mode it is in). The Monosync The same path is taken by incoming data for both SDLC
mode matches the sync character programmed in WR7 and SDLC Loop modes. The reformatted data enters the
and the character assembled in the Receive Sync register 3-bit delay and is transferred to the Receive Shift register.
to establish synchronization.
The SDLC receive operation begins in the hunt phase by
attempting to match the assembled character in the Re-
Synchronization is achieved differently in the Bisync _{ceive Shift Register with the flag pattern in WR7. When the}
mode. Incoming data is shifted to the Receive Shift register _{flag character is recognized, subsequent data is routed}
while the next eight bits of the message are assembled in _{through the same path, regardless of character length.}
the Receive Sync register. If these two characters match
the programmed characters in WR6 and WR7, synchroni- Either the CRC-16 or CRC-SDLC (cyclic redundancy
zation is established. Incoming data can then bypass the check or CRC) polynomial can be used for both Monosync
Receive Sync register and enter the 3-bit delay directly.
and Bisync modes, but only the CRC-SDLC polynomial is
used for SDLC operation. The data path taken for each
The SDLC mode of operation uses the Receive Sync regis- _{mode is also different. Bisync protocol is a byte-oriented}
ter to monitor the receive data stream and to perform zero _{operation that requires the CPU to decide whether or not a}
deletion when necessary; i.e., when five continuous 1s are _{data character is to be included in CRC calculation. An 8-}
received, the sixth bit is inspected and deleted from the data _{bit delay in all Synchronous modes except SDLC is al-}
stream if it is 0. The seventh bit is inspected only if the sixth _{lowed for this process. In SDLC mode, all bytes are includ-}
bit equals one. If the seventh bit is 0, a flag sequence has _{ed in the CRC calculation.}
4.2 ASYNCHRONOUS MODE
In asynchronous communications, data is transferred in
the format shown in Figure 4-3.
Idle State
of Line
1
LSB
0
Start
Bit
Data Field
Stop
Bit(s)
1
Parity 1.5
Bit
2
Figure 4-3. Asynchronous Message Format
UM010901-0601
4-3