Z85233 Datasheet, PDF (218/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

Application Note
SCC in Binary Synchronous Communications
When the Z8002 CPU uses the lower half of the WR0B in channel B of the Z-SCC. For this application, the
Address/Data bus (AD0-AD7 the least significant byte) for Z-SCC registers are located at I/O port address ‘FExx’.
9 ^{byte read and write transactions during I/O operations, The Chip Select signal (/CS0) is derived by decoding I/O}
these transactions are performed between the CPU and address ‘FE’ hex from lines AD15-AD8 of the controller.
I/O ports located at odd I/O addresses. Since the Z-SCC is The Read/Write registers are automatically selected by the
attached to the CPU on the lower half of the A/D bus, its Z-SCC when internally decoding lines AD5-AD1 in Shift
registers must appear to the CPU at odd I/O addresses. To Left mode. To select the Read/Write registers
achieve this, the Z-SCC can be programmed to select its automatically, the Z-SCC decodes lines AD5-AD1 in Shift
internal registers using lines AD5-AD1. This is done either Left mode. The register map for the Z-SCC is depicted in
automatically with the Force Hardware Reset command in Table 1.
WR9 or by sending a Select Shift Left Mode command to
INITIALIZATION
The Z-SCC can be initialized for use in different modes by
setting various bits in its Write registers. First, a hardware
reset must be performed by setting bits 7 and 6 of WR9 to
one; the rest of the bits are disabled by writing a logic zero.
Bisync mode is established by selecting a 16-bit sync
character, Sync Mode Enable, and a Xl clock in WR4. A
data rate of 9600 baud, NRZ encoding, and a data
character length of eight bits are among the other options
that are selected in this example (Table 2).
Note that WR9 is accessed twice, first to perform a
hardware reset and again at the end of the initialization
sequence to enable the interrupts. The programming
sequence depicted in Table 2 establishes the necessary
parameters for the receiver and the transmitter so that,
when enabled, they are ready to perform communication
tasks. To avoid internal race and false interrupt conditions,
it is important to initialize the registers in the sequence
depicted in this application note.
Address
(hex)
FE01
FE03
FE05
FE07
FE09
FE0B
FE0D
FE0F
FE11
FE13
FE15
FE17
FE19
FE1B
FE1D
FE1F
FE21
FE23
FE25
FE27
FE29
FE2B
FE2D
FE2F
FE31
FE33
FE35
FE37
FE39
FE3B
FE3D
FE3F
Table 1. Register Map
Write Register
WR0B
WR1B
WR2
WR3B
WR4B
WR5B
WR6B
WR7B
B DATA
WR9
WR10B
WR11B
WR12B
WR13B
WR14B
WR15B
WR0A
WR1A
WR2
WR3A
WR4A
WR5A
WR6A
WR7A
A DATA
WR9
WR10A
WR11A
WR12A
WR13A
WR14A
WR15A
Read Register
RR0B
RR1B
RR2B
RR3B
B DATA
RR10B
RR12B
RR13B
RR15B
RR0A
RR1A
RR2A
RR3A
A DATA
RR10A
RR12A
RR13A
RR15A
UM010901-0601
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