Z85233 Datasheet, PDF (150/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

Application Note
Interfacing Z80^® CPUs to the Z8500 Peripheral Family
INTERRUPT ACKNOWLEDGE CYCLES
The primary timing differences between the Z80 CPUs and times. Since the Z80 CPUs do not issue either /INTACK or
Z8500 peripherals occur in the Interrupt Acknowledge /RD, external logic must generate these signals.
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cycle. The Z8500 timing parameters that are significant
during Interrupt Acknowledge cycles are listed in Table 16, ^{Generating these two signals is easily accomplished, but}
while the Z80 parameters are listed in Table 17. The ^{the Z80 CPU must be placed into a Wait condition until the}
reference numbers in Tables 16 and 17 refer to Figures 10, ^{peripheral interrupt vector is valid. If more peripherals are}
12 and 13.
added to the daisy chain, additional Wait states may be
necessary to give the daisy chain time to settle. Sufficient
If the CPU and the peripherals are running at different time between /INTACK active and /RD active should be
speeds (as with the Z80H interface), the /INTACK signal allowed for the entire daisy chain to settle.
must be synchronized to the peripheral clock.
Synchronization is discussed in detail under Interrupt ^{Since the Z8500 peripheral daisy chain does not use the}
Acknowledge for Z80H CPU to Z8500/8500A Peripherals. ^{IP flag except during interrupt acknowledge, there is no}
need for decoding the RETI instruction used by the Z80
During an Interrupt Acknowledge cycle, Z8500 peripherals peripherals. In each of the Z8500 peripherals, there are
require both /INTACK and /RD to be active at certain commands that reset the individual IUS flags.
EXTERNAL INTERFACE LOGIC
The following sections discuss external interface logic
required during Interrupt Acknowledge cycles for each
interface type.
peripherals during an Interrupt Acknowledge cycle. The
primary component in this logic is the Shift register
(74LS164), which generates /INTACK, /READ, and /WAIT.
CPU/Peripheral Same Speed
Figure 9 shows the logic used to interface the Z80A CPU
to the Z8500 peripherals and the Z80B CPU to Z8500A
Worst Case
1. TsIA(PC)
ThIA(PC)
2. TdIAi(RD)
5. TwRDA
3. TdRDA(DR)
TsIEI(RDA)
ThIEI(RDA)
TdIEI(IE)
Table 15. Z8500 Timing Parameters Interrupt Acknowledge Cycles
/INTACK Low to PCLK High Setup
/INTACK Low to PCLK High Hold
/INTACK Low to RD (Acknowledge) Low
/RD (Acknowledge) Width
/RD (Acknowledge) to Data Valid
IEI to /RD (Acknowledge) Setup
IEI to /RD (Acknowledge) Hold
IEI to IEO Delay
4 MHz
Min Max
100
100
350
350
250
120
100
150
6 MHz
Min Max
100
100
250
250
180
100
70
100
Units
ns
ns
ns
ns
ns
ns
ns
ns
.
Worst Case
TdC(M1f)
TdM1f(IORQf)
4. TsD(Cr)
Table 16. Z80 CPU Timing Parameters Interrupt Acknowledge Cycles
Clock High to /M1 Low Delay
/M1 Low to /IORQ Low Delay
Data to Clock High Setup
*Z80A: 2TcC + TwCh + TfC - 65
Z80B: 2 TcC + TwCh + TfC - 50
Z80H: 2TcC + TwCh + TfC - 45
4 MHz
Min Max
100
575*
35
6 MHz
Min Max
80
*345
30
8 MHz
Min Max
70
275*
25
Units
ns
ns
ns
UM010901-0601
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