Z85233 Datasheet, PDF (111/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
Register Descriptions
5.1 INTRODUCTION (Continued)
Reset Tx Interrupt Pending Command (101). This com-
mand is used in cases where there are no more characters
to be sent; e.g., at the end of a message. This command
prevents further transmit interrupts until after the next
character has been loaded into the transmit buffer or until
CRC has been completely sent. This command is neces-
sary to prevent the transmitter from requesting an interrupt
when the transmit buffer becomes empty (with Transmit
Interrupt Enabled).
Error Reset Command (110). This command resets the
error bits in RR1. If interrupt on first Rx Character or Inter-
rupt on Special Condition modes is selected and a special
condition exists, the data with the special condition is held
in the Receive FIFO until this command is issued. If either
of these modes is selected and this command is issued be-
fore the data has been read from the Receive FIFO, the
data is lost.
Reset Highest IUS Command (110). This command re-
sets the highest priority Interrupt Under Service (IUS) bit,
allowing lower priority conditions to request interrupts. This
command allows the use of the internal daisy chain (even
in systems without an external daisy chain) and is the last
operation in an interrupt service routine.
Bits 2 through 0: Register Selection Code
On the Z85X30, these three bits select Registers 0 through
7. With the Point High command, Registers 8 through 15
are selected (Table 5-3).
In the multiplexed bus mode, bits D2 through D0 have the
following function.
Bit D2 must be programmed as 0. Bits D1 and D0 select
Shift Left/Right; that is WR0 (1-0)=10 for shift left and WR0
(1-0)=11 for shift right. See Section 2.1.4 for further details
on Z80X30 register access.
5.2.2 Write Register 1 (Transmit/Receive In-
terrupt and Data Transfer Mode Definition)
Write Register 1 is the control register for the various SCC
interrupt and Wait/Request modes. Figure 5-3 shows the
bit assignments for WR1.
Bit 7: WAIT/DMA Request Enable.
This bit enables the Wait/Request function in conjunction
with the Request/Wait Function Select bit (D6).
Write Register 1
D7 D6 D5 D4 D3 D2 D1 D0
Ext Int Enable
Tx Int Enable
Parity is Special Condition
0 0 Rx Int Disable
0 1 Rx Int On First Character or Special Condition
1 0 Int On All Rx Characters or Special Condition
1 1 Rx Int On Special Condition Only
WAIT/DMA Request On
Receive//Transmit
/WAIT/DMA Request Function
WAIT/DMA Request Enable
Figure 5-3. Write Register 1
When programmed to 0, the selected function (bit 6) forces
the /W//REQ pin into the appropriate inactive state (High
for Request, floating for Wait).
When programmed to 1, the state of bit 6 determines the
activity of the /W//REQ pin (Wait or Request).
Bit 6: WAIT/DMA Request Function
When programmed to 0, the Wait function is selected. In
the Wait mode, the /W//REQ pin switches from floating to
Low when the CPU attempts to transfer data before the
SCC is ready.
When programmed to 1, the Request function is selected.
In the Request mode, the /W//REQ pin switches from High
to Low when the SCC is ready to transfer data.
Bit 5: /WAIT//REQUEST on Transmit or Receive
When programmed to 0, the state of the /W//REQ pin is de-
termined by bit 6 and the state of the transmit buffer.
Note: A transmit request function is available on the
/DTR//REQ pin. This allows full-duplex operation under
DMA control for both channels.
5-4
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