Z85233 Datasheet, PDF (22/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
Interfacing the SCC/ESCC
2.2.2 Z80X30 Write Cycle Timing
The write cycle timing for the Z80X30 is shown in
a write cycle. The leading edge of the coincidence of CS1
2 ^{Figure 2-2. The register address on AD7-AD0, as well as High and /DS Low latches the write data on AD7-AD0, as}
the state of /CS0 and /INTACK, are latched by the rising well as the state of R//W.
edge of /AS. R//W must be Low when /DS falls to indicate
/AS
/CS0
/INTACK
AD7 - AD0
R//W
Address
Data Valid
CS1
/DS
Figure 2-2. Z80X30 Write Cycle
UM010901-0601
2-3