Z85233 Datasheet, PDF (162/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

Application Note
The Z180™ Interfaced with the SCC at MHZ
Table 1. Z8018010 Timing Parameters for Opcode Fetch Cycle (Worst Case: Z180 10 MHz)
No Symbol
1 tcyc
2 tCHW
3 tCLW
4 tcf
Parameter
Clock Cycle Period
Clock Cycle High Width
Clock Cycle Low Width
Clock Fall Time
Min
Max
Units
100
ns
7
40
ns
40
ns
10
ns
6 tAD
8 tMED1
9 tRDD1
11 tAH
Clock High to Address Valid
Clock Low to /MREQ Low
Clock Low to /RD Low
Address Hold Time
12 tMED2
15 tDRS
16 tDRH
22 tWRD1
23 tWDD
Clock Low to /MREQ High
Data to Clock Setup
Data Read Hold Time
Clock High to /WR Low
Clock Low to Write Data Delay
24 tWDS
Write Data Setup to /WR Low
25 tWRD2
Clock Low to /WR High
26 tWRP
27 tWDH
/WR Pulse Width
/WR High to Data Hold Time
Note: Parameter numbers in this table are in the Z180 technical manual.
70
ns
50
ns
50
ns
10
ns
50
ns
25
ns
0
ns
50
ns
60
ns
15
ns
50
ns
110
ns
10
ns
T1
T2
Tw
T3
T1
Ø
Address
6
7
/MREQ
8
/RD
11
12
9
Data
11
13
Read Data
15
16
Figure 2. Z180 Memory Read Cycle Timing (One Wait State)
UM010901-0601
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